The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9255 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. ?Pin compatibility with the AD9265, allowing a simple migration up to 16 bits.Applications Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

The ADF7020-1 is a low power, highly integrated FSK/ GFSK/ ASK/ OOK/ GOOK transceiver designed for operation in thelow UHF and VHF bands. The ADF7020-1 uses an externalVCO inductor that allows users to set the operating frequencyanywhere between 135 MHz and 650 MHz. Using the divide-by-2circuit allows users to operate the device as low as 80 MHz.The typical range of the VCO is about 10% of the operatingfrequency. A complete transceiver can be built using a smallnumber of external discrete components, making the ADF7020-1 very suitable for price-sensitive and area-sensitiveapplications.The transmit section contains a VCO and low noisefractional-N PLL with output resolution of <1 ppm. Thisfrequency agile PLL allows the ADF7020-1 to be used infrequency-hopping spread spectrum (FHSS) systems. The VCOoperates at twice the fundamental frequency to reduce spuriousemissions and frequency pulling problems.The transmitter output power is programmable in 63 steps from?20 dBm to +13 dBm. The transceiver RF frequency, channelspacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of2.3 V to 3.6 V and can be powered down when not in useA low IF architecture is used in the receiver (200 kHz),minimizing power consumption and the external componentcount and avoiding interference problems at low frequencies.The ADF7020-1 supports a wide variety of programmablefeatures, including Rx linearity, sensitivity, and IF bandwidth,allowing the user to trade off receiver sensitivity and selectivityfor current consumption, depending on the application. Thereceiver also features a patent-pending automatic frequencycontrol (AFC) loop, allowing the PLL to compensate forfrequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperaturesensor, an external analog input, the battery voltage, or theRSSI signal, which provides savings on an ADC in someapplications. The temperature sensor is accurate to ?10?C overthe full operating temperature range of ?40?C to +85?C. Thisaccuracy can be improved by doing a 1-point calibration atroom temperature and storing the result in memory.Applications Low cost wireless data transfer Wireless medical applications Remote control/security systems Wireless metering Keyless entry Home automation Process and building control

Demonstration circuit 1940A is a low quiescent current, synchronous buck converter featuring the LTC3891EUDC. This demo board converts a 16V to 60V voltage to a 12V at 15A output. The main features of this board include an internal LDO for gate drive power from VIN or EXTVCC, RUN and PGOOD pins, a mode selector that allows the converter to run in constant current mode (CCM), pulse-skipping or Burst Mode® operation, and selectable current limit. The DC1940A supports an adjustable output voltage, soft-start and tracking. The wide input voltage range of 16V to 60V is suitable for double battery automotive and distributed DC power systems where low quiescent current is important.

The LTC6804 is a 3rd generation multicell battery stack monitor that measures up to 12 series connected battery cells with a total measurement error of less than 1.2mV. The cell measurement range of 0V to 5V makes the LTC6804 suitable for most battery chemistries. All 12 cell voltages can be captured in 290?s, and lower data acquisition rates can be selected for high noise reduction.Multiple LTC6804 devices can be connected in series, permitting simultaneous cell monitoring of long, high voltage battery strings. Each LTC6804 has an isoSPI interface for high speed, RF-immune, local area communications. Using the LTC6804-1, multiple devices are connected in a daisy-chain with one host processor connection for all devices. Using the LTC6804-2, multiple devices are connected in parallel to the host processor, with each device individually addressed.Additional features include passive balancing for each cell, an onboard 5V regulator, and 5 general purpose I/O lines. In sleep mode, current consumption is reduced to 4?A. The LTC6804 can be powered directly from the battery, or from an isolated supply.Applications Electric and Hybrid Electric Vehicles Backup Battery Systems Grid Energy Storage High Power Portable Equipment

The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:LTC6954-1: Three LVPECL outputsLTC6954-2: Two LVPECL and one LVDS/CMOS outputsLTC6954-3: One LVPECL and two LVDS/CMOS outputsLTC6954-4: Three LVDS/CMOS outputsEach output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.The LTC6954 also features Linear Technology?s EZSync system for perfect clock synchronization and alignment every time.All device settings are controlled through an SPI-compatible serial port.Applications Clocking High Speed, High Resolution ADCs, DACs?and Data Acquisition Systems Low Jitter Clock Distribution

The LTC6948 is a high performance, low noise, 6.39GHz phase-locked loop (PLL) with a fully integrated VCO, including a reference divider, phase-frequency detector (PFD), ultralow noise charge pump, fractional feedback divider, and VCO output divider.The fractional divider uses an advanced, 4th order ?? modulator which provides exceptionally low spurious levels. This allows wide loop bandwidths, producing extremely low integrated phase noise values.The programmable VCO output divider, with a range of 1 through 6, extends the output frequency range.Applications Wireless Basestations (LTE, WiMAX, W-CDMA, PCS) Microwave Data Links Military and Secure Radio Test and Measurement

The LTC3110 is a 2A bidirectional buck-boost DC/DC regulator with capacitor charger and balancer. Its wide 0.1V to 5.5V capacitor/battery voltage and 1.8V to 5.25V system backup voltage ranges make it well suited to a wide variety of backup applications using supercapacitors or batteries. A proprietary low noise switching algorithm optimizes efficiency with capacitor/battery voltages that are above, below or equal to the system output voltage.The LTC3110 can autonomously transition from charge to backup mode or switch modes based on an external command. Pin-selectable Burst Mode operation reduces standby current and improves light-load efficiency, which combined with a 1?A shutdown current make the LTC3110 ideally suited for backup applications. Additional features include voltage supervisors for direction control and end of charge, and a general purpose comparator with open-collector output for interfacing with a ?C. The LTC3110 is available in thermally enhanced, low profile 24-lead TSSOP and 4mm ? 4mm QFN packages.Applications Supercapacitor Backup Converter and Charger Battery Backup Converter and Charger Servers, RAID Systems RF Systems with Battery/Capacitor Backup

DC1978A: Demo Board for the LTC2974 4-Channel PMBus Power System Manager Featuring Accurate Output Current Measurement.

DC1983A: Demo Board for the LTC5510 1MHz to 6GHz Wideband High Linearity Active Mixer.

The LTC5510 is a high linearity mixer optimized for applications requiring very wide input bandwidth, low distortion, and low LO leakage. The chip includes a double-balanced active mixer with an input buffer and a high speed LO amplifier. The input is optimized for use with 1:1 transmission line baluns, allowing very wideband impedance matching. The mixer can be used for both up- and down-conversion and can be used in wideband systems.The LO can be driven differentially or single-ended and requires only 0dBm of LO power to achieve excellent distortion and noise performance, while also reducing external drive circuit requirements. The LTC5510 offers low LO leakage, greatly reducing the need for output filtering to meet LO suppression requirements.The LTC5510 is optimized for 5V but can also be used with a 3.3V supply with slightly reduced performance. The shutdown function allows the part to be disabled for further power savings.Applications Wideband Receivers/Transmitters Cable Downlink Infrastructure HF/VHF/UHF Mixer Wireless Infrastructure