The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The ?3 dB bandwidth of the ADC input is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/output (GPIO) pins, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9695 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9695 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI) and or PDWN/STBY pin.The AD9695 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +105?C junction temperature range. This product may be protected by one or more U.S. or international patents.Note that, throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Low power consumption per channel. JESD204B lane rate support up to 16 Gbps. Wide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, WCDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation Oscilloscopes Spectrum analyzers Network analyzers Integrated RF test solutions Radars Electronic support measures, electronic counter measures, and electronic counter-counter measures High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths Hybrid fiber coaxial digital reverse path receivers Wideband digital predistortion

The LTC2657 is a family of octal I2C 16-/12-Bit Rail-to-Rail DACs with Integrated 10ppm/?C Max Reference. The DACs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. The LTC2657-L has a full-scale output of 2.5V with the integrated reference and operates from a single 2.7V to 5.5V supply. The LTC2657-H has a full-scale output of 4.096V with the integrated reference and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage.The parts use a 2-wire I2C compatible serial interface. The LTC2657 operates in both the standard mode (maximum clock rate of 100kHz) and the fast mode (maximum clock rate of 400kHz). The LTC2657 incorporates a power-on reset circuit that is controlled by the PORSEL pin. If PORSEL is tied to GND the DACs reset to zero-scale at power-up. If PORSEL is tied to VCC, the DACs reset to mid-scale at power-up.Applications Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment Automotive

The HMC740 is an InGaP Heterojunction Bipolar Transistor (HBT) Gain Block MMIC SMT amplifier covering 0.05 to 3 GHz. Packaged in an industry standard SOT89, the amplifier can be used as a cascadable 50 Ohm RF or IF gain stage as well as a PA or LO driver with up to +18 dBm output power. The HMC740 offers 15 dB of gain with a +40 dBm output IP3 at 100 MHz, and can operate directly from a +5V supply. The HMC740 exhibits excellent gain and output power stability over temperature, while requiring a minimal number of external bias components.Applications Cellular/3G & WiMAX/4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment IF & RF Applications

The AD8368 is a variable gain amplifier (VGA) with analog linear-in-dB gain control that can be used from low frequencies to 800 MHz. Its excellent gain range, conformance, and flatness are attributed to the Analog Devices, Inc. X-AMP? architecture, an innovative technique for implementing high performance variable gain control.The gain range of ?12 dB to +22 dB is scaled accurately to 37.5 dB/V with excellent conformance error. The AD8368 has a 3 dB bandwidth of 800 MHz that is nominally independent of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum gain. The output noise floor is ?143 dBm/Hz, which corresponds to a 9.5 dB noise figure at maximum gain. The single-ended input and output impedances are nominally 50 ?.The gain of the AD8368 can be configured to be an increasing or decreasing function of the gain control voltage depending on whether the MODE pin is pulled to the positive supply or to ground, respectively. When MODE is pulled high, the AD8368 operates as a typical VGA with increasing gain.By connecting MODE to ground and using the on-board rms detector, the AD8368 can be configured as a complete automatic gain control (AGC) system with RSSI. The output power is accurately leveled to the internal default setpoint of 63 mV rms (?11 dBm referenced to 50 ?), independent of the waveform crest factor. Because the uncommitted detector input is available at DETI, the AGC loop can level the signal at the AD8368 output or at any other point in the signal chain over a maximum input power range of 34 dB. Furthermore, the setpoint level can be raised by dividing down the output signal before applying it to the detector.The AD8368 operates from a supply voltage of 4.5 V to 5.5 V and consumes 60 mA of current. It can be fully powered down to <3 mA by grounding the ENBL pin. The AD8368 is fabricated using the Analog Devices proprietary SiGe SOI complementary bipolar IC process. It is available in a 24-lead LFCSP and operates over the industrial temperature range of ?40?C to +85?C. Application boards are available upon request.ApplicationsComplete IF AGC amplifiers Gain trimming and leveling Cellular base stations Point-to-point radio links RF instrumentation Data Sheet, Rev. B, 09/2008

The ADP1764 is a low noise, low dropout (LDO) linear regulator. It is designed to operate from a single input supply with an input voltage as low as 1.10 V without the requirement of an external bias supply to increase efficiency and provide up to 4 A of output current (IOUT).The low 47 mV typical dropout voltage at a 4 A load allows theADP1764 to operate with a small headroom while maintainingregulation and providing better efficiency.The ADP1764 is optimized for stable operation with small 22 ?F ceramic output capacitors. The ADP1764 delivers optimal transientperformance with minimal printed circuit board (PCB) area.The ADP1764 is available in fixed output voltages ranging from 0.55 V to 1.5 V. The output voltage (VOUT) of the adjustableoutput model can be set from 0.5 V to 1.5 V through an external resistor connected between VADJ and ground.The ADP1764 has an externally programmable soft start time by connecting a capacitor to the SS pin. Short-circuit and thermaloverload protection circuits prevent damage in adverse conditions.The ADP1764 is available in a small, 16-lead LFCSP package forthe smallest footprint solution to meet a variety of applications.Applications Regulation to noise sensitive applications such as radio frequency (RF) transceivers, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits, phase-locked loops (PLLs), voltage controlled oscillators (VCOs) and clocking integrated circuits Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies Medical and healthcare Industrial and instrumentation

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB? and SYSREF?) are provided.Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC. The configurable JESD204B output block supports up to 5 Gbps per lane. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. Support for an optional RF clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.Applications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers I/Q demodulation systems Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications

The LTC2664 is a family of four-channel, 16-/12-bit ?10V digital-to-analog converters with integrated precision references. They are guaranteed monotonic and have built-in rail-to-rail output buffers. These SoftSpan? DACs offer five output ranges up to ?10V. The range of each channel is independently programmable, or the part can be hardware-configured for operation in a fixed range.The integrated 2.5V reference is buffered separately to each channel; an external reference can be used for additional range options. The LTC2664 also includes A/B toggle capability via a dedicated pin or software toggle command.The SPI/Microwire-compatible 3-wire serial interface operates on logic levels as low as 1.71V at clock rates up to 50MHz.Applications Optical Networking Instrumentation Data Acquisition Automatic Test Equipment Process Control and Industrial Automation

Demonstration circuit 2918A is a 42V, 5A synchronous step-down SILENT SWITCHER with spread spectrum frequency modulation featuring the LT8636. The demo board is designed for 5V output from a 5.8V to 42V input. The wide input range allows a variety of input sources, such as automotive batteries and industrial supplies. The LT8636 is a compact, low emission, high efficiency, and high frequency synchronous monolithic step-down switching regulator. The proprietary silent switcher architecture minimizes electromagnetic emissions with simplified filter and reduced layout sensitivity. Selectable spread spectrum mode further improves EMI performance, making it perfect solution to the noise sensitive applications. The regulator’s ultralow 2.5μA quiescent current with the output in full regulation enables applications requiring highest efficiency at very light load currents, such as automotive and battery powered portable instruments. Peak current mode control with minimum on-time of as small as 30ns allows high step-down conversion even at high frequency. The LT8636 switching frequency can be programmed either via oscillator resistor or external clock over a 200kHz to 3MHz range. The default frequency of demo circuit 2918A is 2MHz. The SYNC/MODE pin on the demo board 2918A is grounded (JP1 at BURST position) by default for low ripple Burst Mode® operation. To synchronize to an external clock, move the Jump JP1 to SYNC/FCM and apply the external clock to the SYNC terminal on the 2918A. In sync mode, the part runs in forced continuous mode. Without external clock applied, the SYNC/MODE pin is floating, and the part runs in forced continuous mode. This mode offers fast transient response and full frequency operation over a wide load range. Alternatively, move the Jump JP1 to the SPREAD-SPECTRUM, and the SYNC/MODE is tied to INTVCC, the part runs in forced continuous mode with spread spectrum function enabled. To get accurate efficiency measurement, measure the input voltage at the VIN_SENSE and GND terminals, which are Kelvin connected to the input cap C2 through signal traces. The LT8636 is assembled in a 4mmx3mm LQFN package with exposed pads for low thermal resistance. The rated maximum load current is 5A, while derating is necessary for certain input voltage and thermal conditions. The demo board has an EMI filter installed. The red line in Radiated EMI Performance is CISPR25 Class 5 peak limit. The circuit passes the test with a wide margin. To achieve EMI/EMC performance, the input EMI filter is required and the input voltage should be applied at VEMI terminal, and the setup can be referred to the CISPR 25 standards. The LT8636 datasheet gives a complete description of the part, operation and application information. The datasheet must be read in conjunction with this demo manual for demo circuit 2918A. The layout recommendations for low EMI operation and best thermal performance are available in the datasheet section Low EMI PCB Layout and Thermal Considerations and Peak Output Current. Contact ADI applications engineer for support.

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

DC311A Demo Board for: LTC1629 PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator LTC1709-9 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulators