Demonstration circuit DC2342A is a 60V synchronous boost LED controller featuring the LT®3762. It drives a single string of LEDs at 2A up to 32V when VIN is between 7V and 28V. It runs down to 4VIN with reduced ILED and can withstand VIN transients as high as 30V. DC2342A runs at approximately 300kHz switching frequency. Spread spectrum frequency modulation (SSFM) can be turned on with a simple jumper, reducing EMI. DC2342A is designed for high power step-up LED controller applications that require excellent efficiency across the VIN range. This demonstration circuit is protected against both open and short LED conditions, each having its own flag. The LT3762 has an input range from 2.5V to 42V. It has an adjustable switching frequency between 100kHz and 1MHz. Enabling SSFM spreads the switching frequency from fSW down to fSW – 30% for reduced EMI. SSFM speed is set by placing a capacitor from the SSFM pin of the LT3762 to ground, and can be disabled by shorting this pin to GND. DC2342A has a simple jumper option to enable/disable spread spectrum frequency modulation. The LT3762 can be PWM dimmed with an external PWM signal, as well as an internally generated PWM signal. A capacitor from PWM to GND of the LT3762 sets the PWM frequency, while the PWM duty cycle is determined by the voltage on the DIM terminal. Between 0V and 3V, VDIM gives between 0.4% and 97% PWM duty cycle. DC2342A has a jumper that can be set to switch between internally generated PWM signal, externally generated PWM signal, and no PWM signal (100% on). When run with both PWM dimming and spread spectrum enabled, the spread spectrum aligns itself with the PWM signal for flicker free operation. DC2342A can also be analog dimmed by placing a voltage source at either of its two CTRL turrets. Small ceramic input and output capacitors are used to save space and cost. The open LED overvoltage protection uses the IC’s constant voltage regulation loop to regulate the output to approximately 35.5V if the LED string is opened, although it may reach almost 40V peak during the transient caused by an open circuit. There is a protection diode from LED+ to GND to prevent negative ringing during a short-circuit. Undervoltage lockout can be adjusted on the circuit with a few simple resistor choices. Further modifications can be made to DC2342A to reconfigure the circuit from a boost topology to operate as a buck-mode or buck-boost mode LED driver. Please consult the factory for details. The LT3762 data sheet gives a complete description of the part, operation and applications information. The data sheet must be read in conjunction with this Demo Manual for demonstration circuit DC2342A. The LT3762EUFD is assembled in a 28-lead plastic 4mm × 5mm QFN package with a thermally enhanced ground pad. Proper board layout is essential for maximum thermal performance. See the data sheet section Layout Considerations.

The LTC1799 is a precision oscillator that is easy to use and occupies very little PC board space. The oscillator frequency is programmed by a single external resistor (RSET). The LTC1799 has been designed for high accuracy operation (?1.5% frequency error) without the need for external trim components.The LTC1799 operates with a single 2.7V to 5.5V power supply and provides a rail-to-rail, 50% duty cycle square wave output. The CMOS output driver ensures fast rise/fall times and rail-to-rail switching. The frequency-setting resistor can vary from 3k to 1M to select a master oscillator frequency between 100kHz and 33MHz (5V supply). The three-state DIV input determines whether the master clock is divided by 1, 10 or 100 before driving the output, providing three frequency ranges spanning 1kHz to 33MHz (5V supply). The LTC1799 features a proprietary feedback loop that linearizes the relationship between RSET and frequency, eliminating the need for tables to calculate frequency.Applications Low Cost Precision Oscillator Switching Power Supply Clock Reference Clocking Switched Capacitor Filters Fixed Crystal Oscillator Replacement Ceramic Oscillator Replacement

The AD7877 is a 12-bit, successive approximation ADC with a synchronous serial interface and low on resistance switches for driving touch screens. The AD7877 operates from a single 2.7 V to 5.25 V power supply (functional operation to 2.2 V), and features throughput rates of 125 kSPS. The AD7877 features direct battery measurement on two inputs, temperature and touch-pressure measurement.The AD7877 also has an on-board reference of 2.5 V. When not in use, it can be shut down to conserve power. An external reference can also be applied and varied from 1 V to +VCC, with an analog input range of 0 V to VREF. The device includes a shutdown mode that reduces its current consumption to less than 1 ?A.To reduce the effects of noise from LCDs, the acquisition phase of the on-board ADC is controlled via the STOPACQ pin. User-programmable conversion controls include variable acquisition time and first conversion delay. Up to 16 averages can be taken per conversion. There is also an on-board DAC for LCD back-light or contrast control. The AD7877 runs in either slave or master mode using a conversion sequencer and timer. It is ideal for battery-powered systems such as personal digital assistants with resistive touch screens and other portable equipment.The part is available in a 32-lead lead frame chip scale package (LFCSP), and a 25-ball wafer level chip scale package (WLCSP). AD7877W model is qualified for automotive applications.APPLICATIONS Personal digital assistants Smart hand-held devices Touch screen monitors Point-of-sale terminals Medical devices Cell phones Pagers

The ADAU1442?/ ADAU1445?/ ADAU1446 are enhanced audio processors that allow full flexibility in routing all input and output signals. The SigmaDSP? core features full 28-bit processing (56-bit in double-precision mode), synchronous parameter loading for ensuring filter stability, and 100% code efficiency with the SigmaStudio? tools. This DSP allows system designers to compensate for the real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression, limiting, and third-party branded algorithms.The flexible audio routing matrix (FARM) allows the user to multiplex inputs from multiple sources running at various sample rates to or from the SigmaDSP core. This drastically reduces the complexity of signal routing and clocking issues in the audio system. FARM includes up to eight stereo asynchronous sample rate converters (depending on the device model), Sony/Philips Digital Interconnect Format (S/PDIF) input and output, and serial (I2S) and time division multiplexing (TDM) I/Os. Any of these inputs can be routed to the SigmaDSP core or to any of the asynchronous sample rate converters (ASRCs). Similarly, any one of the output signals can be taken from the SigmaDSP core or from any of the ASRC outputs. This routing scheme, which can be modified at any time via control registers, allows for maximum system flexibility.The ADAU1442, ADAU1445, and ADAU1446 differ only in ASRC functionality and packaging. The ADAU1442 / ADAU1445 contain 16 channels of ASRCs and are packaged in TQFP packages, whereas the ADAU1446 contains no ASRCs and is packaged in an LQFP. The ADAU1442 can handle nine clock domains, the ADAU1445 can handle three clock domains, and the ADAU1446 can handle one clock domain.The ADAU1442 / ADAU1445 / ADAU1446 can be controlled in one of two operational modes: the settings of the chip can be loaded and dynamically updated through the SPI/I2C? port, or the DSP can self-boot from an external EEPROM in a system with no microcontroller. There is also a bank of multipurpose (MP) pins that can be used as general-purpose digital I/Os or as inputs to the 4-channel auxiliary control ADC.The ADAU1442 / ADAU1445 / ADAU1446 are supported by the SigmaStudio graphical development environment. This software includes audio processing blocks such as FIR and IIR filters, dynamics processors, mixers, low level DSP functions, and third-party algorithms for fast development of custom signal flows.APPLICATIONS Automotive audio processing Head units Navigation systems Rear-seat entertainment systems DSP amplifiers (sound system amplifiers) Commercial audio processing

The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPSanalog-to-digital converter (ADC) with an on-chip sample-and-holdcircuit designed for low cost, low power, small size,and ease of use. The product operates at a conversion rate ofup to 125 MSPS and is optimized for outstanding dynamicperformance and low power in applications where a smallpackage size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) forcapturing data on the output and a frame clock output (FCO)for signaling a new output byte are provided. Individual-channelpower-down is supported and typically consumes less than 2 mWwhen all channels are disabled. The ADC contains several featuresdesigned to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digitaltest pattern generation. The available digital test patternsinclude built-in deterministic and pseudorandom patterns, alongwith custom user-defined test patterns entered via the serial portinterface (SPI).The AD9253 is available in a RoHS-compliant, 48-lead LFCSP.It is specified over the industrial temperature range of ?40?C to+85?C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 110 mW/channel at 125 MSPS with scalable power options. Pin compatible to the AD9633 12-bit quad ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirementsAPPLICATIONS Medical imaging and nondestructive ultrasound Quadrature radio receivers Diversity radio receivers Optical networking Test equipment

The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.The HMC7043 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 can generate up to seven DCLK and SYSREF clock pairs per the JESD204B/JESD204C interface requirements.The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and LVCMOS, and different bias conditions to adjust for varying board insertion losses. One of the unique features of the HMC7043 is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 ? or 100 ? internal and external termination options. The HMC7043 device features an RF SYNC feature that synchronizes multiple HMC7043 devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephrasing the nested HMC7043 or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase. The HMC7043 is offered in a 48-lead, 7 mm ? 7 mm LFCSP package with an exposed pad connected to ground. Applications JESD204B/JESD204C clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Phase array reference distribution Microwave baseband cards

Demonstration circuit 761 is a low noise regulated charge pump featuring the LTC3204 (Burst Mode operation) in the 2X2 DFN package. There are two assembly versions, DC761A-A and DC761A-B for the LTC3204-5 (5V output) and LTC3204-3.3 (3.3V output) respectively. The DC761A-A produces a regulated 5V output from a 2.7V to 5.5V input. The guaranteed output load current is 150mA for VIN between 3.1V and 5.5V, and 65mA for VIN less than 3.1V. The DC761A-B produces a regulated 3.3V output from a 1.8V to 4.5V input. The guaranteed output current is 50mA from VIN between 1.9V and 4.5V, and 40mA for VIN less than 1.9V. The circuit requires only three tiny 0603 surface mount capacitors and uses minimal board space. No inductor or diodes are needed. The circuit features automatic Burst Mode® operation at light loads to maintain low supply current.

The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:LTC6954-1: Three LVPECL outputsLTC6954-2: Two LVPECL and one LVDS/CMOS outputsLTC6954-3: One LVPECL and two LVDS/CMOS outputsLTC6954-4: Three LVDS/CMOS outputsEach output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.The LTC6954 also features Linear Technology?s EZSync system for perfect clock synchronization and alignment every time.All device settings are controlled through an SPI-compatible serial port.Applications Clocking High Speed, High Resolution ADCs, DACs?and Data Acquisition Systems Low Jitter Clock Distribution

The DC2428A is a two-board demonstration system for the LTC2975 Power System Manager and LTM4644-1 quad 4A μModule regulator. The DC2382A contains all the circuitry needed to use the LTC2975 in a power system and control four power supplies. The DC2363A contains four power supplies (LTM4644-1) that the LTC2975 configures and controls. The DC2363A and DC2382A demo boards together provide a sophisticated 4-channel digitally programmable power supply system.

The LTC7812 is a high performance synchronous Boost+Buck DC/DC switching regulator controller that drives all N-channel power MOSFET stages. It contains independent step-up (boost) and step-down (buck) controllers that can regulate two separate outputs or be cascaded to regulate an output voltage from an input voltage that can be above, below or equal to the output voltage. The LTC7812 operates from a wide 4.5V to 38V input supply range. When biased from the output of the boost regulator, the LTC7812 can operate from an input supply as low as 2.5V after start-up. The 33?A no-load quiescent current extends operating run time in battery-powered systems.Unlike conventional buck-boost regulators, the LTC7812?s cascaded Boost+Buck solution has continuous, nonpulsating, input and output currents, substantially reducing voltage ripple and EMI. The LTC7812 has independent feedback and compensation points for the boost and buck regulation loops, enabling a fast output transient response that can be easily optimized externally.Applications Automotive and Industrial Power Systems High Power Battery Operated Systems