The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit,20/40/65/80 MSPS analog-to-digital converter (ADC). It featuresa high performance sample-and-hold circuit and on-chip voltagereference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 10-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximize flexibilityand minimize system cost, such as programmable clock and dataalignment and programmable digital test pattern generation. Theavailable digital test patterns include built-in deterministic andpseudorandom patterns, along with custom user-defined testpatterns entered via the serial port interface (SPI).A differential clock input with selectable internal 1 to 8 divide ratiocontrols all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, ortwos complement format. A data output clock (DCO) is providedto ensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9609 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (?40?Cto +85?C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingPRODUCT HIGHLIGHTS1. The AD9609 operates from a single 1.8 V analog powersupply and features a separate digital output driver supplyto accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performancefor input frequencies up to 200 MHz and is designed for lowcost, low power, and ease of use.3. A standard serial port interface supports various productfeatures and functions, such as data output formatting,internal clock divider, power-down, DCO and data output(D9 to D0) timing and offset adjustments, and voltagereference modes.4. The AD9609 is packaged in a 32-lead RoHS compliantLFCSP that is pin compatible with the AD9629 12-bit ADCand the AD9649 14-bit ADC, enabling a simple migrationpath between 10-bit and 14-bit converters sampling from20 MSPS to 80 MSPS.

The LT3641 is a dual channel, current mode monolithic buck switching regulator with a power-on reset and a watchdog timer. Both regulators are synchronized to a single oscillator with an adjustable frequency (350kHz to 2.5MHz). At light loads, both regulators operate in low ripple Burst Mode? to maintain high effi ciency and low output ripple.The high voltage channel is a nonsynchronous buck with an internal 2.4A top switch that operates from an input of 4V to 42V and input transient protection to 55V. The low voltage channel operates from an input of 2.5V to 5.5V. Internal synchronous power switches provide high effi ciency without the need of external Schottky diode. Both channels have cycle-by-cycle current limit, providing protection against shorted outputs.The power-on reset and watchdog timeout periods are both adjustable using external capacitors. The window mode watchdog timer fl ags when the ?P pulses group too close together or too far apart.The LT3641 is available in a 28-pin 4mm ? 5mm QFN package and 28-pin TSSOP package. Both packages have an exposed pad for low thermal resistance.Applications Industrial Power Supplies Automotive Electronic Control Units

Digital Potentiometer Development Tools Eval Kit/System MAX5386M, MAX5388, MAX5391, and MAX5393 (Dual 256-Tap,Volatile, Low-Voltage Linear Taper Digital Potentiometers)

Evaluation Board for the LMH6552 High Speed Differential Amplifier

Power Management IC Development Tools Evaluation board based on the ST1PS01EJR 400 mA nano-quiescent synchronous step-down converter

The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for therequired output rates. A second PLL also operates as an integer-N synthesizer anddrives two LVPECL or LVDS output buffers for 106.25 MHzoperation. No external loop filter components are required, thusconserving valuable design time and board space. The AD9572 is available in a 40-lead, 6 mm ? 6 mm lead framechip scale package (LFCSP) and can be operated from a single3.3 V supply. The temperature range is ?40?C to +85?C.APPLICATIONSFiber channel line cards, switches, and routersGigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation

Evaluation Board for the LMP8358

EVAL MOD FOR BQ24200-BQ24205

EVAL MODULE FOR DAC8234

TLV320DAC3120EVM-U Evaluation Module