The ADN4600 is an asynchronous, nonblocking crosspoint switch with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 4.25 Gbps.The receive inputs provide programmable equalization with nine settings to compensate for up to 30 in. of FR4 and programmable pre-emphasis with seven settings to compensate for up to 30 in. of FR4 at 4.25 Gbps.The ADN4600 nonblocking switch core implements an 8 ? 8 crossbar and supports independent channel switching through the I2C control interface. Every channel implements an asynchronous path supporting NRZ data rates from dc to 4.25 Gbps. Each channel is fully independent of other channels. The ADN4600 has low latency and very low channel-to-channel skew.The main application for the ADN4600 is to support switching on the backplane, line card, or cable interface sides of serial links.The ADN4600 is packaged in a 9 mm ? 9 mm, 64-lead LFCSP package and operates from ?40?C to +85?C.APPLICATIONS 1?, 2?, 4? FibreChannel XAUI Gigabit Ethernet over backplane 10GBase-CX4 InfiniBand? 50 ? cables

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

KIT LED DVR C2000 PICCOLO

The HMC7357 is a three-stage GaAs pHEMT MMIC Medium Power Amplifier that operates between 5.5 and 8.5 GHz. The amplifier provides 29 dB of gain and +35 dBm of saturated output power at 34% PAE from a +8V supply. With an excellent Output IP3 of +41.5 dBm, the HMC7357 is ideal for linear applications such as high capacity point-to-point and point-to-multi-point radios or VSAT/SATCOM applications demanding +35 dBm of efficient saturated output power. The RF I/Os are internally matched to 50 Ohms for ease of use. The HMC7357 is packaged in a leadless 5x5 mm plastic surface mount package and is compatible with surface mount manufacturing techniques.Applications Point-to-Point Radios Point-to-Multi-Point Radios VSAT & SATCOM

Evaluation Module for TPS65073 5-Channel Power Management IC

The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time ?-? (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use. The 16 ADC cores features a first-order, CTSD modulator architecture with integrated, background nonlinearity correction logic and self cancelling dither. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. Each ADC has a signal processing tile to filter out of band shaped noise from the ?-? ADC and reduce the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a quadrature digital downconverter (DDC) with multiple finite input response (FIR) decimation filters (decimate by J block), or up to three quadrature DDC channels with averaging decimation filters for data gating applications. Users can configure the Subclass 1 JESD204B based, high speed serialized output in a variety of lane configurations (up to four), depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, TRIG?, and SYNCINB? input pins. The AD9083 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI). The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is specified over the ?40?C to +85?C industrial temperature range.This product is protected by a US patent.APPLICATIONS Millimeter wave imaging Electronic beam forming and phased arrays Multichannel wideband receivers Electronic support measuresPRODUCT HIGHLIGHTS Continuous time, ?-? analog-to-digital converters (ADCs) support signal bandwidths of up to 125 MHz with low power and minimal filtering. Integrated digital processing blocks reduce data payload and lower overall system cost. Configurable JESD204B interface reduces printed circuit board (PCB) complexity. Flexible power-down options. SPI interface controls various product features and functions to meet specific system requirements. Small, 9 mm ? 9 mm, 100-ball CSP_BGA package, simple interface, and integrated digital processing save PCB space.

TPS22968N-Q1 5.5V; 4A; 27mΩ; Dual-Channel Automotive Load Switch Evaluation Module

The HMC892ALP5E is a tunable band-pass filter that features auser selectable pass-band frequency. The 3 dB filter bandwidth isapproximately 8.7%. The 20 dB filter bandwidth is approximately23.8%. The center frequency can be varied between 3.45 GHzand 6.25 GHz by applying an analog tuning voltage between 0 Vand 14 V.This tunable filter can be used as a smaller alternative tophysically large switched filter banks and cavity tuned filters.The HMC892ALP5E has excellent microphonics due to themonolithic design and provides a dynamically adjustablesolution in advanced communications applications. Applications Test and measurement equipment Military radar and electronic warfare (EW)/electronic countermeasures (ECM) Satellite communications (SATCOM) and space Industrial and medical equipment

DC1057A: Demo Board for the LT6411 650MHz Differential ADC Driver/Dual Selectable Gain Amplifier and LTC2249 14-Bit, 80Msps Low Power 3V ADC.

The ADATE324 is a complete, single-chip, quad-channel automatic test equipment (ATE) solution that performs the pin electronics (PE) functions of a driver, a comparator, and an active load (DCL). The device also features a high voltage (VHH) drive capability per chip to support flash memory testing applications. Dedicated 16-bit digital-to-analog converters (DACs) with on-chip calibration registers provide all the necessary dc levels for operation of the device.The voltage driver features three active states: high, low, and terminate mode, as well as a high impedance inhibit state. The inhibit state, in conjunction with the integrated dynamic clamps, facilitates significant attenuation of transmission line reflections when the driver is not actively terminating the line. The open circuit drive capability is ?1.5 V to +4.5 V to accommodate the standard range of ATE and instrumentation applications.The ADATE324 can be used as a quad, single-ended, pin electronics channel or as a dual differential channel. In additional to per channel, high speed window comparators, the ADATE324 provides two programmable threshold differential comparators for differential ATE applications.All dc levels for DCL functions are generated by dedicated on-chip 16-bit DACs. To facilitate accurate programming levels, the ADATE324 also includes an integrated calibration function to correct for gain and offset errors of each functional block. Correction coefficients can be stored on chip, and any values written to the DACs are automatically adjusted using the appropriate correction factors.The ADATE324 uses a serial programmable interface (SPI) bus to program all functional blocks, DACs, and on-chip calibration constants. The device also has an on-chip temperature sensor, and overvoltage and undervoltage fault clamps, for monitoring and reporting the device temperature, and any output pin voltage faults that may occur during operation.For more information on the ADATE324, contact ADATE324@analog.com.APPLICATIONS ATE Semiconductor and board test systems Instrumentation and characterization equipment