The HMC942LP4E is a x2 active broadband frequency multiplier utilizing GaAs pHEMT technology in a leadless RoHS compliant SMT package. When driven by a +4 dBm signal, the multiplier provides +17 dBm typical output power from 13 to 24.6 GHz. The Fo and 3Fo isolations are >20 dBc at 19 GHz. The HMC942LP4E is ideal for use in LO multiplier chains for Pt-to-Pt & VSAT Radios yielding reduced parts count vs. traditional approaches.APPLICATIONS Clock Generation Applications: SONET OC-192 & SDH STM-64 Point-to-Point & VSAT Radios Test Instrumentation Military & Space Sensors

The HMC900LP5E is a 6th order, programmable bandwidth, fully calibrated, dual low pass filter. It features 0 or 10 dB input gain setting and supports arbitrary bandwidths from 3.5 to 50 MHz, and when calibrated, is accurate to ?2.5% of the desired bandwidth. It includes a filter bypass option with a bandwidth of 100 MHz, while retaining gain and common mode settings.Housed in a compact 5x5mm SMT QFN package, the HMC900LP5E requires minimal external components and provides a low cost alternative to more complicated switched discrete filter architectures. Filter calibration for the HMC900LP5E is accomplished with any reference clock rate from 20 to 80 MHz. One time programmable (OTP) memory offers unsurpassed flexibility allowing the user 'set and forget' parameters like gain, and bandwidth setting.Matched filter paths provide excellent quadrature balance, making the HMC900LP5E ideal for I/Q communications applications. The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation.Applications Baseband Filtering for A/D or?D/A Converters? Point-to-Point, Fixed Wireless &?Cellular Base Station Transceivers Integrated Direct Conversion Receiver (DCR)? Software Defined Radio Applications Test & Measurement Equipment

The HMC967LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 15 dB with a noise figure of 2.5 dB and 25 dBc of image rejection across the frequency band. The HMC967LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC967LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The AD603 is a low noise, voltage-controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin-selectable gains of ?11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to 51+ dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor. The input referred noise spectral density is only 1.3 nV/?Hz, and power consumption is 125 mW at the recommended ?5 V supplies.The decibel gain is linear in dB, accurately calibrated, and stable over temperature and supply. The gain is controlled at a high impedance (50 M?), low bias (200 nA) differential input; the scaling is 25 mV/dB, requiring a gain control voltage of only 1 V to span the central 40 dB of the gain range. An overrange and underrange of 1 dB is provided whatever the selected range. The gain control response time is less than 1 ?s for a 40 dB change.The differential gain control interface allows the use of either differential or single-ended positive or negative control voltages. Several of these amplifiers may be cascaded and their gain control gains offset to optimize the system SNR.The AD603 can drive a load impedance as low as 100 ? with low distortion. For a 500 ? load in shunt with 5 pF, the total harmonic distortion for a ?1 V sinusoidal output at 10 MHz is typically ?60 dBc. The peak specified output is ?2.5 V minimum into a 500 ? load.The AD603 uses a patented proprietary circuit topology?the X-AMP?. The X-AMP comprises a variable attenuator of 0 dB to ?42.14 dB followed by a fixed-gain amplifier. Because of the attenuator, the amplifier never has to cope with large inputs and can use negative feedback to define its (fixed) gain and dynamic performance. The attenuator has an input resistance of 100 ?, laser trimmed to ?3%, and comprises a 7-stage R-2R ladder network, resulting in an attenuation between tap points of 6.021 dB. A proprietary interpolation technique provides a continuous gain control function that is linear in dB.The AD603 is specified for operation from ?40?C to +85?C.Applications RF/IF AGC amplifiers Video gain controls A/D range extensions Signal measurements

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k ? 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL? pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL? pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (?40?C to +85?C). This product is protected by a U.S. patent.APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user?s needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation.

The AD737 is a low power, precision, monolithic, true rms-to-dc converter. It is laser trimmed to provide a maximum error of ?0.2 mV ? 0.3% of reading with sine wave inputs. Furthermore, it maintains high accuracy while measuring a wide range of input waveforms, including variable duty cycle pulses and triac (phase) controlled sine waves. The low cost and small physical size of this converter make it suitable for upgrading the performance of non-rms precision rectifiers in many applications. Compared to these circuits, the AD737 offers higher accuracy at equal or lower cost.The AD737 computes the rms value of both the ac and dc input voltages, and is ac-coupled by adding an input capacitor. In this mode, the AD737 can resolve input signal levels of 100 ?V rms or less, despite variations in temperature or supply voltage. High accuracy is maintained for input waveforms with crest factors of 1 to 3 and crest factors at 2.5% or less with respect to full-scale input level.The AD737 has no output buffer amplifier, thereby significantly reducing dc offset errors occurring at the output, which makes the device highly compatible with high input impedance ADCs.Requiring only 160 ?A of power supply current, the AD737 is optimized for use in portable multimeters and other battery-powered applications. In power-down mode, the standby supply current in is typically 25 ?A.The AD737 has both high (1012 ?) and low impedance input options. The high-Z FET input connects high source impedance input attenuators, and a low impedance (8 k?) input accepts rms voltages of up to 0.9 V while operating from the minimum power supply voltage of ?2.5 V. The two inputs can be used either single ended or differentially.The AD737 achieves 1% of reading error bandwidth, exceeding 10 kHz for input amplitudes from 20 mV rms to 200 mV rms, while consuming only 0.72 mW.The AD737 is available in two performance grades. The AD737J and AD737K grades operate over the commercial temperature range of 0?C to 70?C. The AD737JR-5 is tested with supply voltages of ?2.5 V dc. The AD737A grade operates over the industrial temperature range of ?40?C to +85?C. The AD737 is available in two low cost, 8-lead packages: PDIP and SOIC_N.PRODUCT HIGHLIGHTS Computes average rectified, absolute, or true rms value of a signal regardless of waveform. Only one external component, an averaging capacitor, is required for the AD737 to perform true rms measurement. The standby power consumption of 125 ?W makes the AD737 suitable for battery-powered applications.

The AD8038 (single) and AD8039 (dual) amplifiers are high speed (350 MHz) voltage feedback amplifiers with an exceptionally low quiescent current of 1.0 mA/amplifier typical (1.5 mA maximum). The AD8038 single amplifier in the 8-lead SOIC package has a disable feature. Despite being low power and low cost, the amplifier provides excellent overall performance. Additionally, it offers a high slew rate of 425 V/?s and a low input offset voltage of 3 mV maximum.The Analog Devices, Inc., proprietary XFCB process allows low noise operation (8 nV/?Hz and 600 fA/?Hz) at extremely low quiescent currents. Given a wide supply voltage range (3 V to 12 V), wide bandwidth, and small packaging, the AD8038 and AD8039 amplifiers are designed to work in a variety of applications where power and space are at a premium.The AD8038 and AD8039 amplifiers have a wide input common-mode range of 1 V from either rail and swing to within 1 V of each rail on the output. These amplifiers are optimized for driving capacitive loads up to 15 pF. If driving larger capacitive loads, a small series resistor is needed to avoid excessive peaking or overshoot.The AD8039 amplifier is available in a 8-lead SOT-23 package, and the single AD8038 is available in both an 8-lead SOIC and a 5-lead SC70 package. These amplifiers are rated to work over the industrial temperature range of ?40?C to +85?C.Applications Battery-powered instrumentation Filters A/D drivers Level shifting Buffering Photo multipliers

The AD8153 is an asynchronous, protocol agnostic, single-lane 2:1 switch with three differential CML inputs and three differential CML outputs. The AD8159, another member of the Xstream line of products, is suitable for similar applications that require more than one lane.The AD8153 is optimized for NRZ signaling with data rates of up to 3.2 Gbps per port. Each port offers two levels of input equalization and four levels of output pre-emphasis.The device consists of a 2:1 multiplexer and a 1:2 demultiplexer. There are three operating modes: pin mode, serial mode, and mixed mode. In pin mode, lane switching, equalization, and pre-emphasis are controlled exclusively using external pins. In serial mode, an I2C interface is used to control the device and to provide access to advanced features, such as additional pre- emphasis settings and output disable. In mixed mode, the user accesses the advanced features using I2C, but controls lane switching using the external pins.The main application of the AD8153 is to support redundancy on both the backplane side and the line interface side of a serial link. The device has unicast and bicast capability, so it is capable of supporting either 1 + 1 or 1:1 redundancy.Using a mixture of bicast and loopback modes, the AD8153 can also be used to test high speed serial links by duplicating the incoming data and transmitting it to the destination port and test equipment simultaneously.APPLICATIONS Low cost redundancy switch SONET OC48/SDH16 and lower data rates Gigabit Ethernet over backplane Fibre Channel 1.06 Gbps and 2.12 Gbps over backplane Serial RapidIO PCI Express Gen 1 Infiniband over backplane

The AD8195 is an HDMI?/DVI buffer featuring equalized TMDS inputs and preemphasized TMDS outputs, ideal for systems with long cable runs. The AD8195 includes bidirectional buffering for the DDC bus and bidirectional buffering with integrated pull-up resistors for the CEC bus. The DDC and CEC buffers are powered independently of the TMDS buffers so that DDC/CEC functionality can be maintained when the system is powered off.The AD8195 is specified to operate over the ?40?C to +85?C temperature range.PRODUCT HIGHLIGHTS Enables a fully HDMI 1.3a-compliant front panel input. Supports data rates up to 2.25 Gbps, enabling 1080p deep color (12-bit color)? HDMI formats and greater than UXGA (1600 ? 1200) DVI resolutions. Input cable equalizer enables use of long cables; more than 20 meters (24 AWG) at data rates up to 2.25 Gbps. Auxiliary buffer isolates and buffers the DDC bus and CEC line for a single chip,? fully HDMI 1.3a-compliant solution. Auxiliary buffer is powered independently from the TMDS link so that DDC/CEC? functionality can be maintained when the system is powered off.APPLICATIONS Front panel buffers for advanced television (HDTV) sets

The AD8339 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332 / AD8334 / AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4? local oscillator (LO) input that divides this signal and generates the necessary 0? and 90? phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input.Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5? phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45?, then the user can phase align Channel 2 with Channel 1 by choosing the correct code.The mixer outputs are in current form for convenient summation. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the AD8021?or the AD829. Following the current summation, the combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665?(16-bit, 570 kSPS).An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again.The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.APPLICATIONS Medical imaging (CW ultrasound beamforming) Phased array systems Radar Adaptive antennas Communication receivers