The ADP1761 is a low noise, low dropout (LDO) linear regulator. It is designed to operate from a single input supply with an input voltage as low as 1.10 V, without the requirement of an external bias supply to increase efficiency and provide up to 1 A of output current.The low 30 mV typical dropout voltage at a 1 A load allows the ADP1761 to operate with a small headroom while maintaining regulation and providing better efficiency. The ADP1761 is optimized for stable operation with small 10 ?F ceramic output capacitors.The ADP1761 delivers optimal transient performance with minimal board area.The ADP1761 is available in fixed output voltages ranging from 0.9 V to 1.5 V. The output of the adjustable output model can be set from 0.5 V to 1.5 V through an external resistor connected between VADJ and ground.The ADP1761 has an externally programmable soft start time by connecting a capacitor to the SS pin. Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP1761 is available in a small 16-lead LFCSP package for the smallest footprint solution to meet a variety of applications.APPLICATIONS Regulation to noise sensitive applications such as radio frequency (RF) transceivers, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits, phase-locked loops (PLLs), voltage controlled oscillators (VCOs) and clocking integrated circuits Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies Medical and healthcare Industrial and instrumentation Automotive

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The LTC3850 is a high performance dual synchronous step-down switching regulator controller that drives all N-channel power MOSFET stages. A constant-frequency current mode architecture allows a phase-lockable frequency of up to 780kHz. Power loss and supply noise are minimized by operating the two controller output stages out of phase.OPTI-LOOP? compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3850 features a precision 0.8V reference and a power good output indicator. A wide 4V to 24V (28V maximum/30V for LTC3850I) input supply range encompasses most battery chemistries and intermediate bus voltages.Independent TK/SS pins for each controller ramp the output voltages during start-up. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The MODE/PLLIN pin selects among Burst Mode? operation, pulse-skipping mode, or continuous inductor current mode and allows the IC to be synchronized to an external clock.The LTC3850 is available in low profile 28-pin 4mm ? 4mm, 4mm ? 5mm QFN and narrow SSOP packages. Features LTC3850 SSOP-28 and QFN-28 Packages LTC3850-1 ILIM function replaced with an EXTVCC function, SSOP-28 package only LTC3850-2 The LTC3850-2 is identical to the LTC3850-1 SSOP-28, except they have different pin-outs Applications Notebook and Palmtop Computers Portable Instruments Battery-Operated Digital Devices DC Power Distribution Systems

DC572A: Demo Board for the LTC1592 16-Bit SoftSpan DACs with Programmable Output Range.

The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time ?-? (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use. The 16 ADC cores features a first-order, CTSD modulator architecture with integrated, background nonlinearity correction logic and self cancelling dither. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. Each ADC has a signal processing tile to filter out of band shaped noise from the ?-? ADC and reduce the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a quadrature digital downconverter (DDC) with multiple finite input response (FIR) decimation filters (decimate by J block), or up to three quadrature DDC channels with averaging decimation filters for data gating applications. Users can configure the Subclass 1 JESD204B based, high speed serialized output in a variety of lane configurations (up to four), depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, TRIG?, and SYNCINB? input pins. The AD9083 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI). The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is specified over the ?40?C to +85?C industrial temperature range.This product is protected by a US patent.APPLICATIONS Millimeter wave imaging Electronic beam forming and phased arrays Multichannel wideband receivers Electronic support measuresPRODUCT HIGHLIGHTS Continuous time, ?-? analog-to-digital converters (ADCs) support signal bandwidths of up to 125 MHz with low power and minimal filtering. Integrated digital processing blocks reduce data payload and lower overall system cost. Configurable JESD204B interface reduces printed circuit board (PCB) complexity. Flexible power-down options. SPI interface controls various product features and functions to meet specific system requirements. Small, 9 mm ? 9 mm, 100-ball CSP_BGA package, simple interface, and integrated digital processing save PCB space.