The ADF7023 is a very low power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC (Part 15), the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2? or 4?, the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from ?20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allows for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of ?12.2 dBm and ?11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at ?2 MHz offset and 74 dB at ?10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, automatic frequency control (AFC) loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet.A patent pending, image rejection calibration scheme is available through a program download. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare

The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards.The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1.The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance.The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems.The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption.The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller).For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package.APPLICATIONS Wireless sensor networks (WSNs) Home and building automation Asset tracking Process and building control Industrial control Internet of Things (IoT)

The ADF7241 is a highly integrated, low power, and high performance transceiver for operation in the global 2.4 GHz ISM band. It is designed with emphasis on flexibility, robustness, ease of use, and low current consumption. The IC supports the IEEE 802.15.4-2006 2.4 GHz PHY requirements in both packet and data streaming modes. With a minimum number of external components, it achieves compliance with the FCC CFR47 Part 15, ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328 (FHSS, DR > 250 kbps), and ARIB STD T-66 standards.The ADF7241 complies with the IEEE 802.15.4-2006 2.4 GHz PHY requirements with a fixed data rate of 250 kbps and DSSS-OQPSK modulation. The transmitter path of the ADF7241 is based on a direct closed-loop VCO modulation scheme using a low noise fractional-N RF frequency synthesizer. The automatically calibrated VCO operates at twice the fundamental frequency to reduce spurious emissions and avoid PA pulling effects. The bandwidth of the RF frequency synthesizer is automatically optimized for transmit and receive operations to achieve best phase noise, modulation quality, and synthesizer settling time performance. The transmitter output power is programmable from ?20 dBm to +4 dBm with automatic PA ramping to meet transient spurious specifications. An integrated biasing and control circuit is available in the IC to significantly simplify the interface to external PAs.For more information, please refer to the data sheet.Applications Wireless sensor networks Automatic meter reading/smart metering Industrial wireless control Healthcare Wireless audio/video Consumer electronics ZigBee

The ADFS5758 is a single-channel, 16-bit, current/voltage output DAC. The device is functional safety approved for unipolar current output and is a fully compliant item with a systematic capability of SC3, which can be used in safety-related applications up to SIL 2, according to IEC 61508. This arrangement allows a single ADFS5758 to be used to achieve SIL 2 for a nonredundant configuration. The safe state for the ADFS5758 is open circuit/high impedance.The ADFS5758 is a single-channel, voltage and current output digital-to-analog converter (DAC) that operates with a power supply range from ?33 V minimum on AVSS to +33 V maximum on AVDD1 with a maximum operating voltage between the two rails of 60 V. On-chip dynamic power control (DPC) minimizes package power dissipation, which is achieved by regulating the supply voltage (VDPC+) to the VIOUT output driver circuitry from 4.95 V to 27 V using a buck dc-to-dc converter, optimized for minimum on-chip power dissipation. The CHART pin enables a HART? signal to be coupled onto the current output.The device uses a versatile 4-wire serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI?, MICROWIRE?, DSP, and microcontroller interface standards. The interface also features an optional SPI cyclic redundancy check (CRC) and a windowed watchdog timer. The ADFS5758 offers improved diagnostic features from its predecessors, such as an integrated independent 12-bit diagnostic analog-to-digital converter (ADC) that can be used to digitize both internal and external nodes.Product HighIights Functional safety approved to SIL 2/SC3 by T?V Rheinland. Range of advanced diagnostic features, including an integrated ADC for high reliability. DPC using an integrated buck dc-to-dc converter for thermal management. When used with the ADP1031, the ADFS5758 enables eight channel to channel isolated outputs at <2 W dissipated power. Programmable power control (PPC) mode to enable faster settling time (15 ?s typical). Highly robust with output protection from miswire events (?38 V). Applications Process control Actuator control Channel isolated analog outputs Programmable logic controller (PLC) and distributed control system (DCS) applications HART network connectivity

The AD9175 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates up to 12.6 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock?multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9175 features three complex data input channels per RF DAC datapath. Each input channel is fully bypassable. Each data input channel (or channelizer) includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The AD9175 supports an input data rate of up to 3.08 GSPS complex (in-phase/quadrature (I/Q)), or up to 3.4 GSPS noncomplex (real), and is capable of allocating multiple complex input data streams to the assigned channels for individual processing. Each group of three channelizers is summed into a respective main datapath for additional processing when needed. Each main datapath includes an interpolation filter and one 48-bit main NCO ahead of the RF DAC core. Using the modulator switch, the outputs of a main datapath can be either routed to DAC0 alone for operating as a single DAC, or routed to both DAC0 and DAC1 for operating as a dual, intermediate frequency DAC (IF DAC).The AD9175 also supports ultrawide data rate modes that allow bypassing the channelizers and main datapaths to provide maximum data rates of up to 3.4 GSPS as a dual, 11-bit DAC.The AD9175 is available in a 144-ball BGA_ED package.Applications Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammersProduct Highlights A low power, multichannel, dual DAC design reduces power consumption in higher bandwidth and multichannel applications, while maintaining performance. Supports single-band and multiband wireless applications with three bypassable complex data channels per RF DAC, or configurations that use the two main datapaths as two wideband complex data channels when using the built in modulator switch. A maximum complex data rate (per I or Q) of up to 3.08 GSPS with 11-bit resolution, and up to 1.23 GSPS with 16-bit resolution. The AD9175 can be alternatively configured as a dual DAC, with each DAC operating across an independent JESD204B link, at the previously described data rates. Ultrawide bandwidth single DAC modes supporting up to 3.4 GSPS with 11-bit resolution, 12-bit SERDES packing.

The AD9176 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates up to 12.6 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9176 features three complex data input channels per RF DAC datapath. Each input channel is fully bypassable. Each data input channel (or channelizer) includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The AD9176 supports an input data rate of up to a 3.08 GSPS complex (inphase/quadrature (I/Q)), or up to 6.16 GSPS non-complex (real), and is capable of allocating multiple complex input data streams to the assigned channels for individual processing. Each group of three channelizers is summed into a respective main datapath for additional processing when needed. Each main datapath includes an interpolation filter and one 48-bit main NCO ahead of the RF DAC core. Using the modulator switch, the outputs of a main datapath can be either routed to DAC0 alone for operating as a single DAC, or routed to both DAC0 and DAC1 for operating as a dual, intermediate frequency DAC (IF DAC).The AD9176 also supports ultrawide data rate modes that allow bypassing the channelizers and main datapaths to provide maximum data rates of up to 6.16 GSPS as a single, 16-bit DAC, up to 3.08 GSPS as a dual, 16-bit DAC, or up to 4.1 GSPS as a dual, 12-bit DAC.The AD9176 is available in a 144-ball BGA_ED package.Applications Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammersProduct Highlights A low power, multichannel, dual DAC design reduces power consumption in higher bandwidth and multichannel applications, while maintaining performance. Supports single-band and multiband wireless applications with three bypassable complex data channels per RF DAC, or configurations that use the two main datapaths as two wideband complex data channels when using the built in modulator switch. A maximum complex data rate (per I or Q) of up to 3.08 GSPS with 16-bit resolution, and up to 4.1 GSPS with 12-bit resolution. The AD9176 can be alternatively configured as a dual DAC, with each DAC operating across an independent JESD204B link, at the previously described data rates. Ultrawide bandwidth single-DAC modes, supporting up to 6.16 GSPS data rates with 16-bit resolution.

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS The AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9204 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9251 and AD9258 14-bit ADCs, and the AD9231 12-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Handheld scope meters Ultrasound Radar/LIDAR PET/SPECT imaging

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS The AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9204 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9251 and AD9258 14-bit ADCs, and the AD9231 12-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Handheld scope meters Ultrasound Radar/LIDAR PET/SPECT imaging

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS The AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9204 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9251 and AD9258 14-bit ADCs, and the AD9231 12-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Handheld scope meters Ultrasound Radar/LIDAR PET/SPECT imaging

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB? and SYSREF?) are provided.Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC. The configurable JESD204B output block supports up to 5 Gbps per lane. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. Support for an optional RF clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.Applications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers I/Q demodulation systems Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications