The HMC727 is a D-type Flip Flop designed to support data transmission rates of up to 13 Gbps, and clock frequencies as high as 13 GHz. During normal operation, data is transferred to the outputs on the positive edge of the clock. Reversing the clock inputs allows for negative-edge triggered applications. All input signals to the HMC727 are terminated with 50 Ohms to ground on-chip, and maybe either AC or DC coupled.The differential outputs of the HMC727 may be either AC or DC coupled. Outputs can be connected directly to a 50 Ohm to ground terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a nonground DC voltage. The HMC727 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission?up to 13 Gbps Digital Logic Systems up to 13 GHz

The HMC737 is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC737 integrate a resonator, negative resistance device, varactor diode and feature half frequency output. The VCO's phase noise performance is excellent over temperature, shock, and process due to the oscillator's monolithic structure. Power output is +9 dBm typical from a +4.2V supply voltage. The voltage controlled oscillator is packaged in a leadless QFN 4x4 mm surface mount package, and requires no external matching components.APPLICATIONS Point-to-Multi-Point Radios Test Equipment & Industrial Controls SATCOM Military End-Use

The HMC686LP4(E) is a high dynamic range passive MMIC mixer with integrated LO amplifier in a 4x4 SMT QFN package covering 0.7 to 1.1 GHz. Excellent input IP3 performance of +34 dBm for down conversion is provided for 3G & 4G GSM/CDMA applications at an LO drive of 0 dBm. With an input 1 dB compression of +25 dBm, the RF port will accept a wide range of input signal levels. Conversion loss is 7.5 dB typical. The DC to 500 MHz IF frequency response will satisfy GSM/CDMA transmit or receive frequency plans.The HMC686LP4(E) is optimized to high side LO frequency plans for 0.7 - 1.1 GHz RF Band and is pin for pin compatible with the?HMC684LP4(E)?which is a 0.7 - 1.0 GHz converter optimized for low side LO. The HMC686LP4(E) is optimized to low side LO frequency plans for 1.4 - 1.5 GHz RF LTE band applications.APPLICATIONS Cellular/3G & LTE/WiMAX/4G Basestations & Repeaters GSM, CDMA & OFDM Transmitters and Receivers

The HMC822LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC942LP4E is a x2 active broadband frequency multiplier utilizing GaAs pHEMT technology in a leadless RoHS compliant SMT package. When driven by a +4 dBm signal, the multiplier provides +17 dBm typical output power from 13 to 24.6 GHz. The Fo and 3Fo isolations are >20 dBc at 19 GHz. The HMC942LP4E is ideal for use in LO multiplier chains for Pt-to-Pt & VSAT Radios yielding reduced parts count vs. traditional approaches.APPLICATIONS Clock Generation Applications: SONET OC-192 & SDH STM-64 Point-to-Point & VSAT Radios Test Instrumentation Military & Space Sensors

The HMC900LP5E is a 6th order, programmable bandwidth, fully calibrated, dual low pass filter. It features 0 or 10 dB input gain setting and supports arbitrary bandwidths from 3.5 to 50 MHz, and when calibrated, is accurate to ?2.5% of the desired bandwidth. It includes a filter bypass option with a bandwidth of 100 MHz, while retaining gain and common mode settings.Housed in a compact 5x5mm SMT QFN package, the HMC900LP5E requires minimal external components and provides a low cost alternative to more complicated switched discrete filter architectures. Filter calibration for the HMC900LP5E is accomplished with any reference clock rate from 20 to 80 MHz. One time programmable (OTP) memory offers unsurpassed flexibility allowing the user 'set and forget' parameters like gain, and bandwidth setting.Matched filter paths provide excellent quadrature balance, making the HMC900LP5E ideal for I/Q communications applications. The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation.Applications Baseband Filtering for A/D or?D/A Converters? Point-to-Point, Fixed Wireless &?Cellular Base Station Transceivers Integrated Direct Conversion Receiver (DCR)? Software Defined Radio Applications Test & Measurement Equipment

The HMC967LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 15 dB with a noise figure of 2.5 dB and 25 dBc of image rejection across the frequency band. The HMC967LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC967LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The AD1836A is a high performance, single-chip codec that provides three stereo DACs and two stereo ADCs using ADI?s patented multibit ?-? architecture. An SPI? port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1836A operates from a 5 V supply, with provision for a separate output supply to interface with low voltage external circuitry. The AD1836A is available in a 52-lead MQFP (PQFP) package.APPLICATIONS Home theater systems Automotive audio systems DVD recorders Set-top boxes Digital audio effects processors

The AD603 is a low noise, voltage-controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin-selectable gains of ?11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to 51+ dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor. The input referred noise spectral density is only 1.3 nV/?Hz, and power consumption is 125 mW at the recommended ?5 V supplies.The decibel gain is linear in dB, accurately calibrated, and stable over temperature and supply. The gain is controlled at a high impedance (50 M?), low bias (200 nA) differential input; the scaling is 25 mV/dB, requiring a gain control voltage of only 1 V to span the central 40 dB of the gain range. An overrange and underrange of 1 dB is provided whatever the selected range. The gain control response time is less than 1 ?s for a 40 dB change.The differential gain control interface allows the use of either differential or single-ended positive or negative control voltages. Several of these amplifiers may be cascaded and their gain control gains offset to optimize the system SNR.The AD603 can drive a load impedance as low as 100 ? with low distortion. For a 500 ? load in shunt with 5 pF, the total harmonic distortion for a ?1 V sinusoidal output at 10 MHz is typically ?60 dBc. The peak specified output is ?2.5 V minimum into a 500 ? load.The AD603 uses a patented proprietary circuit topology?the X-AMP?. The X-AMP comprises a variable attenuator of 0 dB to ?42.14 dB followed by a fixed-gain amplifier. Because of the attenuator, the amplifier never has to cope with large inputs and can use negative feedback to define its (fixed) gain and dynamic performance. The attenuator has an input resistance of 100 ?, laser trimmed to ?3%, and comprises a 7-stage R-2R ladder network, resulting in an attenuation between tap points of 6.021 dB. A proprietary interpolation technique provides a continuous gain control function that is linear in dB.The AD603 is specified for operation from ?40?C to +85?C.Applications RF/IF AGC amplifiers Video gain controls A/D range extensions Signal measurements

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k ? 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL? pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL? pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (?40?C to +85?C). This product is protected by a U.S. patent.APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user?s needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation.