EVAL MODULE FOR TPS51610-593

The ADN2816 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted.The ADN2816 is available in a compact 5 mm ? 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC rates Fibre Channel, ESCON, Fast Ethernet, SDI, etc. WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers

Demonstration Circuit 2048A is a nanopower buckboost DC/DC with energy harvesting battery life extender featuring the LTC3330. The LTC3330 integrates a high voltage energy harvesting power supply plus a DC/DC converter powered by a primary cell battery to create a single output supply for alternative energy applications. The energy harvesting power supply, consisting of an integrated low-loss full-wave bridge with a high voltage buck converter, harvests energy from piezoelectric, solar or magnetic sources. The primary cell input powers a buck-boost converter capable of operating down to 1.8V at its input. Either DC/DC converter can deliver energy to a single output.

The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A1 are quad-channel digital isolators with an isoPower?, integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler? technology, the dc-to-dc converter provides regulated, isolated power that meets CISPR 32/EN 55032 Class B limits at a full load on a 2-layer printed circuit board (PCB) with ferrites. Popular voltage combinations and the associated output current levels are listed in Table 1 in the data sheet.The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A eliminate the need for a separate, isolated dc-to-dc converter in 500 mW, isolated designs. The iCoupler chip scale transformer technology is used for isolated logic signals and for the magnetic components of the dc-to-dc converter. The result is a small form factor, total isolation solution.The ADuM6420A/ADuM6421A/ADuM6422A/ADuM6423A/ADuM6424A isolators provide four independent isolation channels. See the Pin Configurations and Function Descriptions in the data sheet for additional information.APPLICATIONS RS-232 transceivers Power supply start-up bias and gate drives Isolated sensor interfaces Automotive on-board charger (OBC) and dc to dc Industrial programmable logic controllers (PLCs)1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

Evaluation Board for the LM3253

Demonstration circuit 1529A features the LTC2657 Octal 16-bit DAC with ±4LSB INL error. This device establishes a new board-density benchmark for 16-bit DACs and advances performance standards for output drive, crosstalk and load regulation in single supply, voltage-output multiple DACs.

LM10692EVM Evaluation Module

The LTC1625 is a synchronous step-down switching regulator controller that drives external N-Channel power MOSFETs using few external components. Current mode control with MOSFET VDS sensing eliminates the need for a sense resistor and improves efficiency. The frequency of a nominal 150kHz internal oscillator can be synchronized to an external clock over a 1.5:1 frequency range.Burst Mode? operation at low load currents reduces switching losses and low dropout operation extends operating time in battery-powered systems. A forced continuous mode control pin can assist secondary winding regulation by disabling Burst Mode operation when the main output is lightly loaded.Fault protection is provided by foldback current limiting and an output overvoltage comparator. An external capacitor attached to the RUN/SS pin provides soft start capability for supply sequencing. A wide supply range allows operation from 3.7V (3.9V for LTC1625I) to 36V at the input and 1.19V to VIN at the output.Applications Notebook and Palmtop Computers, PDAs Cellular Telephones and Wireless Modems Battery Chargers Distributed Power

LMZ31530 3V to 14.5V; 30A Step-Down Power Module Evaluation Board