The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages.The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y input is typically less than 0.1% and noise referred to the output is typically less than 100 ?V rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/?s slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns.The versatility of the AD633 is not compromised by its simplicity. The Z input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications.The AD633 is available in 8-lead PDIP and SOIC packages. It is specified to operate over the 0?C to 70?C commercial temperature range (J Grade) or the ?40?C to +85?C industrial temperature range (A Grade).Product Highlights The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead SOIC and PDIP packages. The result is a product that is cost effective and easy to apply. No external components or expensive user calibration are required to apply the AD633. Monolithic construction and laser calibration make the device stable and reliable. High (10 M?) input resistances make signal source loading negligible. Power supply voltages can range from ?8 V to ?18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive.Applications Multiplication, division, squaring Modulation/demodulation, phase detection Voltage-controlled amplifiers/attenuators/filters

The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC core output is connected internally to a noise shaping requantizer (NSR) block. The device supports two output modes that are selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6672 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block is programmed to provide a bandwidth of up to 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6672 can achieve up to 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 11 bits. The AD6672 can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

For a limited time, take a live test drive of the AD6676 by using our?remote evaluation software.The AD6676 is a highly integrated IF subsystem that candigitize radio frequency (RF) bands up to 160 MHz in widthcentered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, theAD6676 relies on a tunable band-pass ?-? ADC with a high oversampling ratio to eliminate the need for band specific IFSAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadraturedigital downconversion followed by selectable decimation filtersreduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interfacesupporting line rates of up to 5.333 Gbps.Applications Wideband cellular infrastructure equipment and repeaters? Point-to-point microwave equipment? Instrumentation? Spectrum and communication analyzers? Software defined radio

The AD6688-3000EBZ supports the AD6688-3000, a 14-bit, 3GSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD6688 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

The AD8122 is a triple, high speed, differential receiver and equalizer that compensates for the transmission losses of UTP and coaxial cables up to 300 meters in length. Various gain stages are summed together to best approximate the inverse frequency response of the cable. Each channel features a high impedance differential input that is ideal for interfacing directly with the cable.The AD8122 has two control inputs for optimal cable compensation, one LPF control input, an input to select between UTP and coax cable, and an output offset adjust input. The cable compensation inputs are used to compensate for different cable lengths; the VPEAK input controls the amount of high frequency peaking and the VGAIN input adjusts the broadband flat gain, which compensates for the flat cable loss. The VFILTER input controls the cutoff frequency of output lowpass filters on each channel. Selection between UTP and coaxial cable compensation responses is determined by the binary COAX/UTP?input, which can be left floating in UTP applications. The VOFFSET pin allows the dc voltage at the output to be adjusted, which can be useful in dc-coupled systems.For added flexibility, the gains of each channel can be set to x1 or x2 using the associated GAIN control pins.The AD8122 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is rated to operate over the extended temperature range of ?40?C to +85?C.APPLICATIONS Keyboard-video-mouse (KVM) Digital signage RGB video over UTP cables Professional video projection and distribution HD video Security video

The AD8124 is a triple, high speed, differential receiver and equalizer that compensates for the transmission losses of UTP and coaxial cables up to 200 meters in length. Various gain stages are summed together to best approximate the inverse frequency response of the cable. Logic circuitry inside the AD8124 controls the gain functions of the individual stages so that the lowest noise can be achieved at short-to-medium cable lengths. This technique optimizes its performance for low noise, short-to-medium range applications, while at the same time provides the high gain bandwidth required for longer cable equalization (up to 200 meters). Each channel features a high impedance differential input that is ideal for interfacing directly with the cable.The AD8124 has three control pins for optimal cable compensation, as well as an output offset adjust pin. Two voltage-controlled pins are used to compensate for different cable lengths; the VPEAK pin controls the amount of high frequency peaking and the VGAIN pin adjusts the broadband flat gain, which compensates for the low frequency flat cable loss.For added flexibility, an optional pole adjustment pin, VPOLE, allows movement of the pole locations, allowing for the compensation of different gauges and types of cable as well as variations between different cables and/or equalizers. The VOFFSET pin allows the dc voltage at the output to be adjusted, adding flexibility for dc-coupled systems.The AD8124 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is rated to operate over the extended temperature range of ?40?C to +85?C.APPLICATIONS Keyboard-video-mouse (KVM) Digital signage RGB video over UTP cables Professional video projection and distribution HD video Security video

The AD8155 is an asynchronous, protocol-agnostic, dual-lane 2:1 switch with a total of six differential CML inputs and six differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output pre-emphasis, programmable output levels, and loss-of-signal detection.The nonblocking switch-core of the AD8155 implements a 2:1 multiplexer and 1:2 demultiplexer per lane and supports independent lane switching through the two select pins, SEL[1:0]. Each port is a two-lane link. Every lane implements an asynchronous path supporting dc to 6.5 Gbps NRZ data, fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew.The main application of the AD8155 is to support redundancy on both the backplane and the line interface sides of a serial link. The demultiplexing path implements unicast and bicast capability, allowing the part to support either 1+1 or 1:1 redundancy.The AD8155 is also suited for testing high speed serial links because of its ability to duplicate incoming data. In a port monitoring application, the AD8155 can maintain link connectivity with a pass-through connection from Port C to Port A while sending a duplicate copy of the data to test equipment on Port B.The rich feature set of the AD8155 can be controlled either through external toggle pins or by setting on-chip control registers through the I2C? interface.ApplicationsLow cost redundancy switchSONET OC48/SDH16 and lower data ratesRXAUI, 4x Fibre Channel, Infiniband , and GbE over backplaneOIF CEI 6.25 Gbps over backplaneSerial data-level shift2-/4-/6-lane equalizers or redrivers

The AD8188 (G = 1) is a high speed, single-supply, triple 2-to-1 multiplexer. It offers -3 dB small signal bandwidth of 350 MHz and -3 dB large signal bandwidth of 300 MHz, along with a slew rate in excess of 1000 V/?s. With -84 dB of all hostile crosstalk and -95 dB off isolation, the part is well suited for many high speed applications. The differential gain and differential phase error of 0.05% and 0.05? respectively, along with 0.1 dB flatness to 70 MHz, make the AD8188 ideal for professional and component video multiplexing. The part offers 4 ns switching time, making them an excellent choice for switching video signals, while consuming less than 20 mA on a single 5 V supply (100 mW). The device has a high speed disable feature that sets the outputs into a high impedance state. This allows the building of larger input arrays while minimizing off-channel output loading. The device is offered in a 24-lead TSSOP.

The AD8209A is a single-supply difference amplifier ideal for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage. The input common-mode voltage range extends from ?2 V to +50 V at a single 5 V supply. The AD8209A is qualified per AEC-Q100 specifications. The amplifier offers enhanced input overvoltage and ESD protection, and includes electromagnetic interference (EMI) filtering.Automotive applications demand robust, precision components for improved system control. The AD8209A provides excellent ac and dc performance, minimizing errors in the application. Typical offset and gain drift in the MSOP package are less than 5 ?V/?C and ?5 ppm/?C, respectively. The device also delivers a minimum common-mode rejection ratio (CMRR) of 80 dB from dc to 10 kHz.The AD8209A features an externally accessible 100 k? resistor at the output of the preamplifier (A1) that can be used for low-pass filtering and for establishing gains other than 14 V/V.Applications High-side current sensing Motor controls Solenoid controls Power management Low-side current sensing Diagnostic protection