The LTC2337-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with fully differential inputs. Operating from a single 5V supply, the LTC2337-18 has a ?10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2337-18 achieves ?4LSB INL maximum, no missing codes at 18-bits with 100dB SNR.The LTC2337-18 has an on-board single-shot capable reference buffer and low drift (20ppm/?C max) 2.048V temperature compensated reference. The LTC2337-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 500ksps throughput with no cycle latency makes the LTC2337-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2337-18 dissipates only 35mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2337-18 to 300?W for further power savings during inactive periods.Applications Programmable Logic Controllers Industrial Process Control High Speed Data Acquisition Portable or Compact Instrumentation ATE

ADS7829 Evaluation Module

Dual Input, Far Field Noise Suppression Microphone Amplifier

HD3SS460EVM-SRC high-speed passive crosspoint switch evaluation module

Bluetooth and MSP430 Audio Source Reference Design Board

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm ? 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.Applications Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

MODULE EVAL BQ20Z90/29330/29412

EVALUATION MODULE

TPS65400EVM Evaluation Module

Demo board DC2783A features the LT3040, a 200mA high performance, robust voltage reference/DAC buffer. LT3040 has ultralow output noise, ultrahigh power supply rejection ratio (PSRR) and low dropout voltage for powering noise sensitive, high accuracy systems. DC2783A has two inputs: V+ and VIN. V+ supplies power to the buffer, operating over a range from 2V to 20V. VIN is the regulation set-point for the output with a range from 0V to 15V. Current limit is programmable by connecting a resistor, R3, from ILIM to GND. The ILIM can also serve as a current monitor pin with a range from 0V to 300mV. LT3040 has fast start capability. Connecting FS pin across an input low pass filter resistor, R2, fast starts the LT3040. Fast start circuitry is typically triggered active if VFS − VIN ≥ 100mV and stays active until VFS – VIN ≤ 7mV. If fast start functionality is not needed, connect FS to VIN by setting R2 to 0Ω and applying the input voltage at FS. LT3040 has a fault flag to indicate faults at the output. Built-in protection includes reverse battery protection, reverse current protection, internal current limit with foldback and thermal limit with hysteresis. The LT3040 datasheet gives a complete description of the part, operation and applications information. The datasheet must be read in conjunction with this Demo Manual for demonstration circuit DC2783A. The LT3040 is assembled in a 12-lead MSOP and a 10-lead (3mm x 3mm) plastic DFN package with an exposed pad on the bottom-side of the IC. Proper board layout is essential for maximum thermal performance.