Basic Evaluation Kit for the KH3 433 MHz Transmitter Module

The AD5310R?/ AD5311R, members of the nanoDAC? family, are low power, single-channel, 10-bit buffered voltage-out DACs. The devices include a 2.5 V, 2 ppm/?C internal reference. The output span can be programmed to be 0 V to VREF or 0 V to 2 ? VREF. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The devices are available in 10-lead MSOP packages.The AD5310R / AD5311R also incorporate a power-on resetcircuit that ensures that the DAC output powers up to zeroscaleand remains there until a valid write takes place. Thedevice contains a power-down feature that reduces the currentconsumption of the device to 2 ?A at 5 V while in power-downmode.The AD5310R / AD5311R use a versatile SPI or I2C interface,including an asynchronous RESET pin and a VLOGIC pin, allowing 1.8 V compatibility.PRODUCT HIGHLIGHTS High Relative Accuracy (INL): ?0.5 LSB maximum. Low Drift 2.5 V On-Chip Reference: 5 ppm/?C maximum temperature coefficient.APPLICATIONS Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources Optical modules

Power Management IC Development Tools LM2852Y-2.5 EVAL BOARD

Power Management IC Development Tools 2A 500/1500kHz Synchronous SIMPLE SWITCH

3-A Active Bus Termination/DDR Memory DC/DC Converter

The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

10A, 12V Input, 1.8V Output Synchronous Buck Converter using the TPS40192 and NexFET? MOSFETs

The AD9520-2 provides a multioutput clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHzto 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520-2 serial interface supports both SPI and I2C?ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.The AD9520-2 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-2.Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.The AD9520-2 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.The AD9520-2 is specified for operation over the standardindustrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

The LTC6405 is a very low noise, low distortion, fully differential input/output amplifier optimized for 5V, single supply operation. The LTC6405 input common mode range is rail-to-rail, while the output common mode voltage is independently adjustable by applying a voltage on the VOCM pin. This makes the LTC6405 ideal for level shifting signals with a wide common mode range for driving 12-bit to 16-bit single supply, differential input ADCs.A 2.7GHz gain-bandwidth product results in 65dB linearity for 50MHz input signals. The LTC6405 is unity gain stable and the closed-loop bandwidth extends from DC to 800MHz. The output voltage swing extends from near-ground to 4V, to be compatible with a wide range of ADC converter input requirements. The LTC6405 draws only 18mA, and has a hardware shutdown feature which reduces current consumption to 400?A.The LTC6405 is available in a compact 3mm ? 3mm 16?pin leadless QFN package, as well as an 8-lead MSOP package, and operates over a ?40?C to 85?C temperature range.Applications Differential Input ADC Driver Single-Ended to Differential Conversion Level-Shifting Ground-Referenced Signals Level-Shifting VCC-Referenced Signals High-Linearity Direct Conversion Receivers

TPS65021EVM Evaluation Module