Demonstration circuit 2278A features the LTC4281 hot swap controller. The LTC4281 is well suited to high power applications because the precise monitoring capability and accurate current limiting reduces the extremes in which both loads and power supplies must safely operate. Non-volatile configuration allows for flexibility in the autonomous generation of alerts and response to faults.

The LTC2380-24 is a low noise, low power, high speed 24-bit successive approximation register (SAR) ADC with an integrated digital averaging filter. Operating from a 2.5V supply, the LTC2380-24 has a ?VREF fully differential input range with VREF ranging from 2.5V to 5.1V. The LTC2380- 24 consumes only 28mW and achieves ?3.5ppm INL maximum and no missing codes at 24 bits.The LTC2380-24 has an easy to use integrated digital averaging filter that can average 1 to 65536 conversion results real-time, dramatically improving dynamic range from 101dB at 1.5Msps to 145dB at 30.5sps. No separate programming interface or configuration register is required.The high speed SPI-compatible serial interface supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisychain mode. The LTC2380-24 automatically powers down between conversions, reducing power dissipation at lower sampling rates.Applications Seismology Energy Exploration Medical Imaging High Speed Data Acquisition Industrial Process Control ATE

The LTC2380-24 and LTC2368-24 are low power, low noise, high speed, 24-bit SAR ADCs with an integrated digital averaging filter that operates from a single 2.5V supply. The demo manual refers to the LTC2380-24 but applies to both parts, the only difference being that the LTC2380-24 has fully differential inputs and the LTC2368-24 has pseudo-differential inputs. The LTC2380-24 has –117dB THD, consumes only 28mW and achieves ±4ppm INL max with no missing codes at 24 bits. The DC2289A demonstrates the DC and AC performance of the LTC2380-24 in conjunction with the DC590 or DC2026 QuikEval™ and DC890 PScope™ data collection boards. Use the DC590 or DC2026 to demonstrate DC performance such as peak-to-peak noise and DC linearity. Use the DC890 if precise sampling rates are required or to demonstrate AC performance such as SNR, THD, SINAD and SFDR. The Demonstration Circuit 2289A is intended to show recommended grounding, component placement and selection, routing and bypassing for this ADC.

The AD9106 TxDAC? and waveform generator is a high performance, quad digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform generation with a direct digital synthesizer (DDS). The DDS is a 12-bit output, up to 180 MHz master clock sinewave generator with a 24-bit tuning word allowing 10.8 Hz/LSB frequency resolution. The DDS has a single frequency output for all four DACs and independent programmable phase shift outputs for each of the four DACs.SRAM data can include directly generated stored waveforms, amplitude modulation patterns applied to DDS outputs, or DDS frequency tuning words.An internal pattern control state machine allows the user to program the pattern period for all four DACs as well as the start delay within the pattern period for the signal output on each DAC channel.Registers accessed using the serial peripheral interface (SPI) configure the digital waveform generator and load patterns into the SRAM.There are gain adjustment factors and offset adjustments applied to the digital signals on their way into the four DACs.The AD9106 offers exceptional ac and dc performance and supports DAC sampling rates up to 180 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9106 make it well suited for portable and low power applications.Applications Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9121 is a dual, 14-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency.The AD9121 TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9121 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies (IF). Proprietary DAC output switching technique enhances dynamic performance. Current outputs are easily configured for various single-ended or differential circuit topologies. Flexible LVDS digital interface allows the standard 28-wire bus to be reduced to one-half of the width.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

The AD9119/AD9129 are high performance, 11-/14-bit RF digital-to-analog converters (DACs) supporting data rates up to 2.85 GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode? or 2? interpolation. The high dynamic range and bandwidth enable multicarrier generation up to 4.2 GHz.In baseband mode, wide bandwidth capability combines with high dynamic range to support from 1 to 158 contiguous carriers for CATV infrastructure applications. A choice of two optional 2? interpolation filters is available to simplify the postreconstruction filter by effectively increasing the DAC update rate by a factor of 2. In Mix-Mode operation, the AD9119/AD9129 can reconstruct RF carriers in the second and third Nyquist zone while still maintaining exceptional dynamic range up to 4.2 GHz. The high performance NMOS DAC core features a quad-switch architecture that enables industry-leading direct RF synthesis performance with minimal loss in output power. The output current can be programmed over a range of 9.5 mA to 34.4 mA.The AD9119/AD9129 include several features that may further simplify system integration. A dual-port, source synchronous LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the integrity of the interface. On-chip delay locked loops (DLLs) optimize timing between different clock domains.A serial peripheral interface (SPI) configures the AD9119/ AD9129 and monitors the status of readback registers. The AD9119/AD9129 are manufactured on a 0.18 ?m CMOS process and operates from +1.8 V and ?1.5 V supplies. It is supplied in a 160-ball chip scale package ball grid array.Product Highlights High dynamic range and signal reconstruction bandwidth support RF signal synthesis of up to 4.2 GHz. Dual-port interface with double data rate (DDR) LVDS data receivers supports 2850 MSPS maximum conversion rate. Manufactured on a CMOS process; a proprietary switching technique enhances dynamic performance.Applications Broadband communications systems CMTS/VOD Wireless infrastructure: W-CDMA, LTE, point-to-point Instrumentation, automatic test equipment (ATE) Radar, jammers

Demonstration circuit 1587A is a boost converter optimized for relatively high impedance, very low voltage input power sources. It allows a user to quickly evaluate the LTC3105 boost converter and LDO regulator. Capable of operating with an input voltage as low as 250mV and as high as 5V, the circuit features maximum power point control (MPPC). Jumpers on the circuit board allow the user to select several MPPC voltages, three boost output voltages and three LDO regulator output voltages. Also included are jumpers for shutdown and for selecting an external pull-up voltage for the power good status output. Terminals are provided for input and output connections, power good output and external power good supply input, shutdown input, and provisions for external MPPC resistor and MPPC diode input. This demonstration board is especially designed for low power solar cell applications.

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The LT5517 is a 40MHz to 900MHz quadrature demodulator optimized for high linearity receiver applications where high dynamic range is important. It is suitable for communications receivers where an RF or IF signal is directly converted into I and Q baseband signals with a bandwidth up to 130MHz. The LT5517 incorporates balanced I and Q mixers, LO buffer amplifiers and a precision, broadband quadrature generator derived from an on-chip divide-by-two circuit.The superior linearity and low noise performance of the LT5517 is achieved across its full frequency range. A well-balanced divide-by-two circuit generates precision quadrature LO carriers to drive the I mixer and the Q mixer. Consequently, the outputs of the I-channel and the Q-channel are well matched in amplitude, and their phases are 90? apart. The LT5517 also provides excellent 50? impedance matching at the 2XLO port across its entire frequency range.Applications Wireless Infrastructure High Linearity Direct Conversion I/Q Receiver High Linearity I/Q Demodulator