The HMC892ALP5E is a tunable band-pass filter that features auser selectable pass-band frequency. The 3 dB filter bandwidth isapproximately 8.7%. The 20 dB filter bandwidth is approximately23.8%. The center frequency can be varied between 3.45 GHzand 6.25 GHz by applying an analog tuning voltage between 0 Vand 14 V.This tunable filter can be used as a smaller alternative tophysically large switched filter banks and cavity tuned filters.The HMC892ALP5E has excellent microphonics due to themonolithic design and provides a dynamically adjustablesolution in advanced communications applications. Applications Test and measurement equipment Military radar and electronic warfare (EW)/electronic countermeasures (ECM) Satellite communications (SATCOM) and space Industrial and medical equipment

The HMC951A is a compact gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), in-phase quadrature (I/Q) downconverter in a RoHS compliant package that operates from 5.6 GHz to 8.6 GHz. This device provides a small signal conversion gain of 13 dB with a noise figure of 2 dB and an image rejection of 32 dBc. The HMC951A uses a low noise amplifier (LNA) followed by an image mixer that is driven by a local oscillator (LO) buffer amplifier. The image reject mixer eliminates the need for a filter following the LNA and removes thermal noise at the image frequency. The IF1 and IF2 mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of unwanted sideband. The HMC951A is a smaller alternative to hybrid style, single sideband (SSB) downconverter assemblies, and it eliminates the need for wire bonding by allowing the use of surface-mount manufacturing techniques.The HMC951A is available in 4 mm ? 4 mm, 24-lead lead frame chip scale package (LFCSP) and operates over the ?40?C to +85?C temperature range. An evaluation board for the HMC951A is also available upon request. Applications Point to point and point to multipoint radios Military radars, electronic warfare, and electronic intelligence Satellite communications Sensors

The EV-21569-SOM with low-cost evaluation and rapid prototyping of the ADSP-2156× Family (ADSP-21562/21563/21565/21566/21567/21569) of SHARC+ audio processors. It features the processor, memory, and power portions of the design and provides an easy-to-use plug-n-play reference design with all the key interfaces made available on three connectors for marrying to either the EV-SOMCRR-EZKIT carrier board or a custom carrier board. The EV-21569-SOM and EV-SOMCRR-EZKIT boards may be purchased as a bundle (EV-21569-EZKIT), providing fast and easy evaluation of the processor core and system peripherals/interfaces. The EV-21569-SOM module requires the CrossCore® Embedded Studio (CCES) development tools to enable developers to achieve faster time to market. The development environment aids advanced application code development and debug, such as: Create, compile, assemble, and link application programs written in C++, C, and assembly Load, run, step, halt, and set breakpoints in application programs Read and write data and program memory Read and write core and peripheral registers When used without the EV-SOMCRR-EZKIT carrier board, the EV-21569-SOM board requires an external in-circuit emulator (ICE-1000 or ICE-2000) be connected to the JTAG header.

The EV-21593-SOM enables evaluation and rapid prototyping of designs featuring the ADSP-2159x Family (ADSP-21591/ADSP-21593) of SHARC audio processors. It provides an easy-to-use plug-n-play reference design with expansion capabilities to interface to custom hardware ahead of the release of the processor itself. When the EV-21593-SOM board is plugged into the EV-SOMCRR-EZKIT carrier board, the resulting EZ-KIT® evaluation system (EV-21593-EZKIT) can be used for fast and easy evaluation of the processor core and system peripherals/interfaces. The EV-21593-SOM enables rapid prototyping for a wide range of applications, including immersive 3D sound and personal audio zones (PAZ), automotive active and road noise cancellation (ANC/RNC), voice-based user-interfaces and in-car communications (ICC), engine sound synthesis (ESS) and electric vehicle warning sound systems (EVWSS/AVAS). Additional applications include professional audio and soundbars / home AVRs (with 3D Object and Multi-Channel Audio) and enhanced conferencing systems. ADI offers several software modules (e.g., AEC/NR, microphone beamforming, pitch shifting, harmonic generators, wave players etc.), as well as complete software solutions that can be licensed, where users can develop/evaluate their audio and voice processing applications. ADI also offers 3rd party surround sound solutions that can be licensed on ADI’s SHARC processor families. Please visit ADI’s Software Solutions page for more information. The EV-21593-SOM module utilizes the CrossCore® Embedded Studio (CCES) development tools to enable developers to achieve faster time to market. The development environment aids advanced application code development and debug, such as: Create, compile, assemble, and link application programs written in C++, C, and assembly Load, run, step, halt, and set breakpoints in application programs Read and write data and program memory Read and write core and peripheral registers

The HMC1119 is a broadband, highly accurate, 7-bit digitalattenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dBattenuation control range in 0.25 dB steps.The HMC1119 is implemented in a silicon process, offeringvery fast settling time, low power consumption, and high ESDrobustness. The device features safe state transitions and isoptimized for excellent step accuracy and high linearity overfrequency and temperature range. The RF input and output areinternally matched to 50 ? and do not require any externalmatching components. The design is bidirectional; therefore,the RF input and output are interchangeable.The HMC1119 has an on-chip regulator that can support a widesupply operating range from 3.3 V to 5.0 V with no performancechange in electrical characteristics. The HMC1119 incorporates adriver that supports serial (3-wire) and parallel controls of theattenuator.The HMC1119 comes in a RoHS-compliant, compact, 4 mm ?4 mm LFCSP package.A fully populated evaluation board is available.Applications Cellular infrastructure Microwave radios and very small aperture terminals (VSATs) Test equipment and sensors IF and RF designs

The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).The AD9172 is available in a 144-ball BGA_ED package.PRODUCT HIGHLIGHTS Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.APPLICATIONS Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammers

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.?The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.Product Highlights Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers