The AD9520-31 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.The AD9520 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.The AD9520 is specified for operation over the standard industrial range of ?40?C to +85?C.1The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it is referring to that specific member of the AD9520 family.Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

The AD9522-11 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.The AD9522 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.The AD9522 is specified for operation over the standard industrial range of ?40?C to +85?C.The AD9520-1 is an equivalent part to the AD9522-1 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-1 is used, it is referring to that specific member of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

The 10 clock outputs of the AD9544 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9544 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Appliations SyncE and GPS synchronization and jitter cleanup Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

DC1266A-A: Demo Board for the LTC2453 Ultra-Tiny, Differential, 16-Bit ∆Σ ADC With I2C Interface

Demonstration circuit 1267A is a step-up DC/DC regulator featuring the LTC3125EDCB and is ideally suited for pulsed load applications where the input current needs to be limited. Demonstration circuit 1267A is configured for 500mA maximum input current limit and can handle pulsed load currents of up to 2A, with duty cycles of up to 15%. The input voltage range is 3.3V ±10%.

The LTC1520 is a high speed, precision differential line receiver that can operate at data rates as high as 50Mbps. A unique architecture provides very stable propagation delays and low skew over a wide input common mode, input overdrive and ambient temperature range. Propagation delay is 18ns ?3ns, while typically tPLH/tPHL skew is 500ps and channel-to-channel skew is 400ps.Each receiver translates differential input levels (VID ? 100mV) into valid CMOS and TTL output levels. Its high input resistance (?18k) allows many receivers to be connected to the same driver. The receiver outputs go into a high impedance state when disabled.Protection features include thermal shutdown and a controlled maximum short-circuit current (50mA max) that does not oscillate in and out of short-circuit mode. Input resistance remains ?18k when the device is unpowered or disabled, thus allowing the LTC1520 to be hot swapped into a backplane without loading the data lines.The LTC1520 operates from a single 5V supply and draws 12mA of supply current. The part is available in a 16-lead narrow SO package.Applications High Speed Backplane Interface Line Collision Detector PECL and LVDS Line Receivers Level Translator Ring Oscillator Tapped Delay Line

DC1273A: Demo Board for LT1938 - 25V, 2.2A, 2.8MHz Step-Down Switching Regulator

Demonstration circuit 1294A exercises four adjustable linear regulators in parallel using the LT3080. A small 20 mΩ ballast resistor is required for parallel operation. A short PCB trace can easily serve that purpose. The paralleled devices provide up to 4.4A of output current at 3.3V. Architected as a precision current source and voltage follower, the LT3080 can be used in many applications requiring high current, adjustability to zero output, and no heat sink. The device brings out the collector of the pass transistor to allow low dropout operation when used with multiple supplies. The LT3080's output voltage can be programmed to any level between 0V and 36V; however the demo board has a reduced input voltage range from 3.8V to 25V due to the input capacitor voltage rating.

Demonstration circuit DC1297B features the LTM4612EV, an EN55022 Class B certified synchronous step-down power module. The board accepts an input voltage from 5V to 36V and delivers a jumper programmable output voltage of 3.3V, 5V or 12V. The rated load current is 5A for 3.3V and 5V output voltages, or 3A for a 12V output. Current derating is necessary for certain VIN, VOUT, and thermal conditions.