The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).The AD9172 is available in a 144-ball BGA_ED package.PRODUCT HIGHLIGHTS Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.APPLICATIONS Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammers

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The ADP2138 and ADP2139 are high efficiency, low quiescent current, synchronous step-down dc-to-dc converters. The ADP2139 has the additional feature of an internal discharge switch. The total solution requires only three tiny external components. When the MODE pin is set high, the buck regulator operates in forced PWM mode, which provides low peak-to-peak ripple for power supply noise sensitive loads at the expense of light load efficiency. When the MODE pin is set low, the buck regulator automatically switches operating modes, depending on the load current level. At higher output loads, the buck regulator operates in PWM mode. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving light load efficiency.The ADP2138/ADP2139 operate on input voltages of 2.3 V to 5.5 V, which allows for single lithium or lithium polymer cell, multiple alkaline or NiMH cell, PCMCIA, USB, and other standard power sources. The maximum load current of 800 mA is achievable across the input voltage range.The ADP2138/ADP2139 are available in fixed output voltages of 3.3 V, 3.0 V, 2.8 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and 0.8 V. All versions include an internal power switch and synchronous rectifier for minimal external part count and high efficiency. The ADP2138/ADP2139 have internal soft start and they are internally compensated. During logic controlled shutdown, the input is disconnected from the output and the ADP2138/ADP2139 draw 0.2 ?A (typical) from the input source.Other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup. The ADP2138/ADP2139 are available in a 6-ball wafer level chip scale package (WLCSP).Applications PDAs and palmtop computers Wireless handsets Digital audio, portable media players Digital cameras, GPS navigation units

The ADP2165/ADP2166 are high efficiency, current modecontrol, step-down dc-to-dc regulators with an integrated 19 m?high-side FET and a 15 m? synchronous rectified FET. TheADP2165/ADP2166 combine a small size, 4 mm ? 4 mm LFCSPpackage with an accurate current limit, resulting in a smallerinductor size and a high power density, point of load solution.Key features include precision enable, power-good monitor,and output voltage tracking to facilitate robust sequencing.The switching frequency can be programmed from 250 kHzto 1.4 MHz, or it can be fixed at 620 kHz or 1.2 MHz. Thesynchronization function allows the switching frequency tosynchronize to an external clock, minimizing theelectromagnetic interference (EMI) of the system.The ADP2165/ADP2166 are designed to be extremely flexiblewith the addition of a minimal amount of external componentsto program soft start and control loop compensation.he ADP2165/ADP2166 are supplied from an input voltage of2.7 V to 5.5 V. Output voltage options include 3.3 V, 2.5 V, 1.8 V,1.5 V, 1.2 V, or 1.0 V fixed outputs and adjustable options capableof supporting an output voltage range from 0.6 V to 90% of theinput voltage. Protection features include undervoltage lockout(UVLO), overvoltage protection (OVP), overcurrent protection(OCP), and thermal shutdown (TSD) for robust performance.The ADP2165/ADP2166 operate over the ?40?C to +125?Cjunction temperature range and are available in a 24-leadLFCSP package.Applications Point of load regulation Communications and networking High end consumer Industrial, instrumentation, and healthcare

The ADP2386 is a synchronous step-down, dc-to-dc regulator with an integrated 44 m?, high-side power MOSFET and an 11 m?, synchronous rectifier MOSFET to provide a high efficiency solution in a compact 4 mm ? 4 mm LFCSP package. This device uses a peak current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. The switching frequency of the ADP2386 can be programmed between 200 kHz to 1.4 MHz. To minimize system noise, the synchronization function allows the switching frequency to be synchronized to an external clock.The ADP2386 requires minimal external components and operates from an input voltage of 4.5 V to 20 V. The output voltage can be adjusted from 0.6 V to 90% of the input voltage and delivers up to 6 A of continuous current. Each IC draws less than 110 ?A current from the input source when it is disabled.This regulator targets high performance applications that require high efficiency and design flexibility. External compensation and an adjustable soft start function provide design flexibility. The power-good output and precision enable input provide simple and reliable power sequencing.Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), short-circuit protection (SCP) and thermal shutdown (TSD).The ADP2386 operates over the ?40?C to +125?C junction temperature range and is available in a 24-lead, 4 mm ? 4 mm LFCSP package.Applications Communications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion DC-to-dc point-of-load applications

The ADP2443 is synchronous step-down, dc-to-dc regulator with an integrated 98 m?, high-side power metal oxide semicon-ductor field effect transistor (MOSFET) and a 35 m?, synchronous rectifier MOSFET to provide a high efficiency solution in a compact 4 mm ? 4 mm LFCSP package. The regulators operate from an input voltage range of 4.5 V to 36 V. The output voltage can be adjusted down to 0.6 V and deliver up to 3 A of continuous current. The fast 50 ns minimum on time allows the regulators convert high input voltage to low output voltage at high frequency.The ADP2443 uses an emulated current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. The switching frequency of the ADP2443 can be programmed from 200 kHz to 1.8 MHz. The synchronization function allows the switching frequency be syn-chronized with an external clock to minimize the system noise.The ADP2443 targets high performance applications that require high efficiency and design flexibility. External compensation and an adjustable soft start function provide design flexibility. The power-good output and precision enable input provide simple and reliable power sequencing.Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), short-circuit protection (SCP), and thermal shutdown (TSD).The ADP2443 operates over the ?40?C to +125?C operating junction temperature range and is available in a 24-lead, 4 mm ? 4 mm LFCSP package.Applications Intermediate power rail conversion Multicell battery powered systems Process control and industrial automation Healthcare and medical Networking and servers

The ADP5034 combines two high performance buck regulators and two low dropout (LDO) regulators in a small, 24-lead 4 mm ? 4 mm LFCSP (QFN) to meet demanding performance and board space requirements.The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light-load efficiency.The two bucks operate out of phase to reduce the input capaci-tor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5034 LDOs extend the battery life of portable devices. The ADP5034 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.Regulators in the ADP5034 are activated though dedicated enable pins. The default output voltages can be externally set in the adjustable version, or factory programmable in the fixed voltage version, and can be set to a wide range of preset valuesAPPLICATIONSPower for processors, ASICS, FPGAs, and RF chipsetsPortable instrumentation and medical devicesSpace constrained devices

The ADP5053 combines four high performance buck regulators, a supervisory circuit, a watchdog timer, and a manual reset in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15.0 V with no preregulators.Channel 1 and Channel 2 integrate high-side power MOSFET and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration can provide a single output with up to 8 A of current.Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 1.2 A.The switching frequency of the ADP5053 can be programmed or synchronized to an external clock. The ADP5053 contains a precision enable pin on each channel for easy power-up sequencing or adjustable UVLO threshold.The ADP5053 contains supervisory circuits that monitor the voltage level. The watchdog timer can generate a reset if the WDI pin is not toggled within a preset timeout period. Processor reset mode or system power on/off switch mode can be selected for manual reset functionality.Applications Small cell base stations FPGA and processor applications Security and surveillance Medical applications

The ADP5054 combines four high performance buck regulators in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages of up to 15.5 V with no preregulators.Channel 1 and Channel 2 integrate high-side power metal-oxide semiconductor field effect transistors (MOSFETs) and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and to deliver a programmable output current of 2 A, 4 A, or 6 A. Combining Channel 1 and Channel 2 in a parallel configuration provides a single output with up to 12 A of current.Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 2.5 A. Combining Channel 3 and Channel 4 in a parallel configuration can provide a single output with up to 5 A of current.The switching frequency of the ADP5054 can be programmed or synchronized to an external clock from 250 kHz to 2 MHz, and an individual ?? frequency configuration is available for each channel.The ADP5054 contains an individual precision enable pin on each channel for easy power-up sequencing. The internal low 1/f noise reference is implemented in the ADP5054 for noise sensitive applications.Applications FPGA and processor applications Small cell base stations Security and surveillance Medical applications