The ADF4360-3 is a fully integrated integer-N synthesizer andvoltage controlled oscillator (VCO). The ADF4360-3 is designedfor a center frequency of 1750 MHz. In addition, there is adivide-by-2 option available, whereby the user gets an RF output of between 800 MHz and 975 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.?

The ADF4360-8 is an integrated integer-N synthesizer and voltagecontrolled oscillator (VCO). The ADF4360-8 center frequencyis set by external inductors. This allows a frequencyrange of between 65 MHz to 400 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.?

The ADF4371 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave voltage controlled oscillator (VCO) design allows frequencies from 62.5 MHz to 32 GHz to be generated.The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. To suppress the unwanted products of frequency multiplication, a harmonic filter exists between the multipliers and the output stages of RF16x and RF32x.Control of all on-chip registers is through a 3-wire interface. The ADF4371 operates with analog and digital power suppliesranging from 3.15 V to 3.45 V, and 5 V for the VCO power supply. The ADF4371 also contains hardware and software power-down modes. APPLICATIONS Wireless infrastructure (multicarrier global system for mobile communication (MC-GSM), 5 G) Test equipment and instrumentation Clock generation Aerospace and defense

The ADF5610 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference source. The wideband microwave voltage controlled oscillator (VCO) design permits frequency operation from 7300 MHz to 14600 MHz at a single radio frequency (RF) output. A series of frequency dividers with a differential frequency output allows operation from 57 MHz to 14600 MHz. Analog and digital power supplies for the PLL circuitry range from 3.1 V to 3.5 V, and the VCO supplies are between 4.75 V and 5.25 V. The charge pump supply voltage can be extended up to 3.6 V for improved frequency band overlap and extended upper frequency range.The ADF5610 has an integrated VCO with a fundamental frequency of 3650 MHz to 7300 MHz. These frequencies are internally doubled and routed to the RFOUT pin. An additional differential output allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to generate RF output frequencies as low as 57 MHz. A simple 3?wire serial port interface (SPI) provides control of all on-chip registers. To conserve power, this divider block can be disabled when not needed through the SPI interface. Likewise, the output power for both the single-ended output and the differential output are programmable via the VCO register settings. The ADF5610 also contains various power-down modes for the VCO circuitry and PLL circuitry.The integrated phase detector (PD) and delta-sigma (?-?) modulator, capable of operating at up to 100 MHz, permit wide loop bandwidths and fast frequency tuning with a typical spurious level of ?100 dBc.With phase noise levels from ?115 dBc/Hz at 7.3 GHz to ?109 dBc/Hz at 14.6 GHz, the ADF5610 is equipped to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. The low phase noise floor eliminates any contribution to modulator and mixer noise floor in transmitter applications.The ADF5610 is a PLL with integrated VCO. The device features an innovative programmable performance technology that enables the ADF5610 to tailor current consumption and corresponding noise performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved phase noise performance.Additional features of the ADF5610 include approximately 3 dBof RFOUT gain control in 1.5 dB steps and 5 dB of control onthe differential port in approximately 2.5 dB steps. Finally, the ?-?modulator with exact frequency mode enables users to generateoutput frequencies with 0 Hz frequency error.APPLICATIONSMilitary and defenseTest equipmentClock generationWireless infrastructureSatellite and very small aperture terminal (VSAT)Microwave radio

The ADF5902 is a 24 GHz transmitter (Tx) monolithic microwaveintegrated circuit (MMIC) with an on-chip, 24 GHz voltagecontrolled oscillator (VCO). The VCO features a fractional-Nfrequency synthesizer with waveform generation capability withprogrammable grid array (PGA) and dual transmitter channelsfor radar systems. The on-chip, 24 GHz VCO generates the24 GHz signal for the two transmitter channels and the localoscillator (LO) output. Each transmitter channel contains apower control circuit. There is also an on-chip temperaturesensor.Control of all the on-chip registers is through a simple, 4-wireserial peripheral interface (SPI).The ADF5902 comes in a compact, 32-lead, 5 mm ? 5 mmLFCSP package. Applications Automotive radars Industrial radars Microwave radar sensors

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of ?20 dBm to +13 dBm and ?20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM??Cortex?-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the?IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm ? 6 mm, 40-lead LFCSP and a 7 mm ? 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is ?40?C to +85?C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_CON is a programmable value that configures the internal LDO voltage that provides bias for the PA. For additional information on these bit settings, see the ADF7030-1 Software Reference Manual, which is the detailed programming guide for the device.Applications IEEE 802.15.4g (MR-FSK PHY)? Wireless M-Bus (EN 13757-4) Smart metering Security and building automation? Active tag asset tracking Industrial control Wireless sensor networks (WSNs)

The ADuCM322 is a fully integrated, single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM? Cortex?-M3 processor and integral flash for code and data.The ADC on the ADuCM322 provides 12-bit, 1 MSPS data acquisition on up to 16 input balls. Additionally, chip temperature and supply voltages can be measured.The ADC input voltage range is 0 V to VREF. A sequencer is provided, which allows a user to select a set of ADC channels to measure in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a user selectable rate. Up to eight VDACs are provided with output ranges that are programmable to one of two voltage ranges.The ADuCM322 can be configured so that the digital and analog outputs retain their output voltages through a watchdog or software reset sequence. Thus, a product can remain functional even while the ADuCM322 is resetting itself.The ADuCM322 has a low power ARM Cortex-M3 processor and a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on-chip are 2 ? 128 kB Flash/EE memory blocks and 32 kB of SRAM. The flash comprises two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block.The ADuCM322 operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In normal operating mode, the ADuCM322 digital core consumes about 300 ?A per MHz.The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADuCM322 ideal for 10G, 40G, and 100G optical applications. In addition, the nonerasable kernel code plus flags in user flash provide assistance by allowing user code to robustly switch between the two blocks of user flash code and data spaces.The ADuCM322 integrates a range of on-chip peripherals that can be configured under software control, as required in the application. These peripherals include 1 ? UART, 2 ? I2C, and 2 ? SPI serial input/output communication controllers, GPIO, 32-element PLA, three general-purpose timers, plus a wake-up timer and system watchdog timer. A 16-bit PWM with seven output channels is also provided.GPIO balls on the device power up in high impedance input mode. In output mode, the software chooses between open-drain mode and push-pull mode. The pull-up resistors can be disabled and enabled in software. In GPIO output mode, the inputs can remain enabled to monitor the balls. The GPIO balls can also be programmed to handle digital or analog peripheral signals; in such cases, the ball characteristics are matched to the specific requirement.A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM322. Access is via the ARM serial wire debug port (SW-DP). On-chip factory firmware supports in-circuit serial download via MDIO. These features are incorporated into a QuickStart? development system, supporting this precision analog microcontroller family.APPLICATIONS Optical networking

The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.The conversion process and data acquisition are controlled using ASYNC and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of ASYNC and conversion is also initiated at this point. There are no pipeline delays associated with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V to VREFA input or a 0 V to 2 ? VREFA with either straight binary or twos complement output coding. The conversion time is determined by the ASCLK frequency because it is also used as the master clock to control the conversion.The DAC section of the AD5590 comprises sixteen 12-bit DACs divided into two groups of eight. Each group has an on-chip reference. The on-board references are off at power-up, allowing the use of external references. The internal references are enabled via a software write.The AD5590 incorporates a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain powered up at this level until a valid write takes place. The DAC contains a power-down feature that reduces the current consumption of the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a user-programmable code: zero scale, midscale, or full scale.The AD5590 contains eight low noise, single-supply amplifiers. These amplifiers can be used for signal conditioning for the ADCs, DACs, or other independent circuitry, if required.APPLICATIONS Optical Line Cards (Monitoring and Control) Base Stations General Purpose Analog I/O Monitoring and control

The AD5593R has eight input/output (I/O) pins, which can beindependently configured as digital-to-analog converter (DAC)outputs, analog-to-digital converter (ADC) inputs, digital outputs,or digital inputs. When an I/O pin is configured as an analogoutput, it is driven by a 12-bit DAC. The output range of theDAC is 0 V to VREF or 0 V to 2 ? VREF. When an I/O pin isconfigured as an analog input, it is connected to a 12-bit ADCvia an analog multiplexer. The input range of the ADC is 0 V toVREF or 0 V to 2 ? VREF. The I/O pins can also be configured tobe general-purpose, digital input or output (GPIO) pins. Thestate of the GPIO pins can be set or read back by accessing theGPIO write data register and GPIO read configuration registers,respectively, via an I2C write or read operation.The AD5593R has an integrated 2.5 V, 20 ppm/?C reference thatis turned off by default and an integrated temperature indicatorthat gives an indication of the die temperature. The temperaturevalue is read back as part of an ADC read sequence.The AD5593R is available in 16-lead TSSOP and LFCSP, as wellas a 16-ball WLCSP, and operates over a temperature range of?40?C to +105?C.Applications Control and monitoring General-purpose analog and digital I/O

The AD5668 device is a low power, octal, 16-bit, buffered voltage-output DAC. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The AD5668 and AD5628 are available inboth a 4 mm ? 4 mm LFCSP and a 16-lead TSSOP, while theAD5648 is available in both a 14-lead and 16-lead TSSOP.The AD5628/AD5648/AD5668 have an on-chip reference withan internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 havea 1.25 V 5 ppm/?C reference, giving a full-scale output rangeof 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 havea 2.5 V 5 ppm/?C reference, giving a full-scale output range of5 V. The on-board reference is off at power-up, allowing the useof an external reference. The internal reference is enabled via asoftware write.The part incorporates a power-on reset circuit that ensures that theDAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1,AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) andremains powered up at this level until a valid write takes place.The part contains a power-down feature that reduces the currentconsumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or allDAC channels. The outputs of all DACs can be updated simultaneouslyusing the LDAC function, with the added functionalityof user-selectable DAC channels to simultaneously update. Thereis also an asynchronous CLR that updates all DACs to a userprogrammablecode?zero scale, midscale, or full scale.The AD5628/AD5648/AD5668 utilize a versatile 3-wire serialinterface that operates at clock rates of up to 50 MHz and iscompatible with standard SPI?, QSPI?, MICROWIRE?, andDSP interface standards. The on-chip precision output amplifierenables rail-to-rail output swing.Product Highlights Octal, 12-/14-/16-bit DAC. On-chip 1.25 V/2.5 V, 5 ppm/?C reference. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP. Power-on reset to 0 V or midscale. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Applications Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators