Demonstration circuit 1852A is a combined step-up and step-down DC/DC converter, using the LTC3536 monolithic synchronous buck-boost regulator in the MSOP package. The DC1852A has wide input voltage range of 1.8V to 5.5V and is capable of delivering up to 1A of output current. The output voltage of the DC1852A can be set as low as 1.8V and can go as high as 5.5V. DC1852A supports two operation modes: fixed-frequency pulse-width modulation (PWM) and Burst Mode® operation.

BOARD EVAL FOR AD5665 LFCSP

Demonstration circuit 2094A shows the proper way to drive the LTC®2348 family of ADCs. The LTC2348/LTC2347/LTC2343 are low noise, high speed, simultaneous sampling 16-/18-bit successive approximation register (SAR) ADCs. The demo manual refers to the LTC2348-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. The LTC2348-18 has a flexible SoftSpan™ interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. An internal 2.048V reference and 2X buffer simplify basic operation while an external reference can be used to increase the input range and the SNR of the ADC.

The AD5674/AD5674R/AD5679/AD5679R are low power,?16-channel, 12-/16-bit, buffered voltage output, digital-to-analog converters (DACs) that include a 2.5 V, 2 ppm/?C internal reference (enabled by default), and a gain select pin, resulting in a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The?devices operate from a single, 2.7 V to 5.5 V supply range and?are guaranteed monotonic by design. The AD5674/AD5674R/AD5679/AD5679R are available in a 28-lead lead frame chip scale package (LFCSP) and incorporate a power-on reset (POR) circuit that ensures that the DAC outputs power up to and remains at zero-scale or midscale until a valid write. The AD5674/AD5674R/AD5679/AD5679R contain a power-down mode that reduces the current?consumption to 2 ?A typical.Product Highlights High channel density: 16 channels in 4 mm ? 4 mm?LFCSP. High relative accuracy (integral nonlinearity (INL)) ?4 LSB maximum. Low drift, 2.5 V, on-chip reference.Applications Optical transceivers Base station power amplifiers Process control (programmable logic controller (PLC) input/output cards) Industrial automation Data acquisition systems

DC1133A-C: Demo Board for LTC2240-12 12-Bit, 170Msps ADC

The LTC4279 is an autonomous single port power sourcing equipment (PSE) controller designed for use in IEEE 802.3at Type 1, Type 2 and LTPoE++ compliant Power over Ethernet (PoE) systems. The LTC4279 provides fully autonomous IEEE 802.3 and LTPoE++ compliant operation without a microcontroller. The LTC4279 simplifies PSE implementation, requiring only a single supply and a small number of passive support components.The LTC4279 delivers lowest-in-industry heat dissipation by utilizing a low-RDS(ON) external MOSFET and a 0.1? sense resistor, eliminating the need for expensive heat sinks and increasing efficiency.PD discovery uses a proprietary dual-mode 4-point detection mechanism ensuring excellent immunity from false PD detection. Midspan PSEs are supported with physical layer classification and a 2.5 second backoff timer.Legacy and custom PDs are supported with pin-selectable LEGACY and UltraPWR modes. LEGACY mode detects and powers pre-IEEE specification PDs. UltraPWR mode aggressively turns on and powers custom PDs requiring high inrush and/or operational currents.Applications PoE PSE Endpoints (Switch/Router) PoE Midspan Power Injectors Power Forwarders Femto Cells Security Systems

The ADN4620/ADN4621 are dual-channel, signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 2.5 Gbps with very low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals, such as current mode logic (CML).The ADN4620/ADN4621 include a refresh mechanism to monitor the input and output states and ensure that they remain the same in the absence of data transitions (for example, at power-on). For lower power consumption and high speed operation with low jitter, the isolator circuits rely on 1.8 V supplies, while 3.3 V supplies are used for LVDS receivers to support the full common-mode range with an input voltage range (input common mode plus differential input voltage) of 0 V to 2.4 V per Table 2 in the data sheet.The devices are fully specified over a wide industrial temperature range and are available in a compact SSOP package with 5.3 mm creepage (for reinforced insulation at ac mains voltages).APPLICATIONS Analog front-end isolation Data plane isolation Isolated high speed clock and data links Multigigabit serialization/deserialization (SERDES) PCB-to-PCB optical replacement (for example, short reach fiber)Protected by U.S. Patents 7,075,329; 9,941,565; and 10,205,442. Other patents are pending.

The ADCMP600, ADCMP601, and ADCMP602 are very fast comparators fabricated on Analog Devices? proprietary XFCB2 process. These comparators are exceptionally versatile and easy to use. Features include an input range from ? 0.5 V to VCC + 0.2 V, low noise TTL-/CMOS-compatible output drivers, and latch inputs with adjustable hysteresis and/or shutdown inputs.The devices offer 5 ns propagation delay with 10 mV overdrive on 3 mA typical supply current.A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a ?0.5 V to +2.8 V input signal range up to a +5.5 V positive supply with a ?0.5 V to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions on the ADCMP602 support a wide input signal range while still allowing independent output swing control and power savings.The TTL-/CMOS-compatible output stage is designed to drive up to 5 pF with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided with a unique single-pin control option.The ADCMP600 is available in both 5-lead SC70 and SOT-23 packages, the ADCMP601 is available in a 6-lead SC70 package, and the ADCMP602 is available in 8-lead MSOP and LSCFP packages.Applications High Speed Instrumentation Clock and Data Signal Restoration Logic Level Shifting or Translation Pulse Spectroscopy High Speed Line Receivers Threshold Detection Peak and Zero-crossing Detectors High Speed Trigger Circuitry Pulse-width Modulators Current-/voltage-controlled Oscillators Automatic Test Equipment (ATE)

Demonstration circuit 2046A-E is a PoE powered device (PD) with an isolated power supply using synchronous flyback topology, featuring the LT4276 and ideal diode bridge controller (LT4321).

The LTC2000 is a family of 16-/14-/11-bit 2.5Gsps current steering DACs with exceptional spectral purity.The single (1.25Gsps mode) or dual (2.5Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.25Gbps using a 625MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock.Additional features such as pattern generation, LVDS loopout and junction temperature sensing simplify system development and testing.A serial peripheral interface (SPI) port allows configuration and read back of internal registers. Operating from 1.8V and 3.3V supplies, the LTC2000 consumes 2.2W at 2.5Gsps and 1.3W at 1.25Gsps.Applications Broadband Communication Systems DOCSIS CMTS Direct RF Synthesis Radar Instrumentation Automatic Test Equipment