The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells? FDD and TDD active antenna systems? Microwave, nonline of sight (NLOS) backhaul systems

The ADV3226/ADV3227 are high speed 16 ? 16 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth greater than 750 MHz and channel switch times of less than 20 ns with 1% settling.The ADV3226/ADV3227 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3226 has a gain of +1 and the ADV3227 has a gain of +2. They both operate on voltage supplies of ?5 V while consuming only 118 mA (ADV3226) and 133 mA (ADV3227) of idle current. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3226/ADV3227 are available in the 100-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) Data communications Telecommunications

The ADCMP606 and ADCMP607 are very fast comparatorsfabricated on XFCB2, an Analog Devices, Inc., proprietaryprocess. These comparators are exceptionally versatile and easyto use. Features include an input range from VEE ? 0.5 V toVCCI + 0.2 V, low noise, CML-compatible output drivers, andTTL-/CMOS-compatible latch inputs with adjustable hysteresisand/or shutdown inputs.The devices offer 1.25 ns propagation delay with 2.5 ps rmsrandom jitter (RJ). Overdrive and slew rate dispersion aretypically less than 50 ps.A flexible power supply scheme allows the devices to operatewith a single +2.5 V positive supply and a ?0.5 V to +2.7 Vinput signal range up to a +5.5 V positive supply with a ?0.5 Vto +5.7 V input signal range. The ADCMP607 features splitinput/output supplies with no sequencing restrictions tosupport a wide input signal range with independent outputswing control and power savings.The CML-compatible output stage is fully back-matched forsuperior performance. The comparator input stage offers robustprotection against large input overdrive, and the outputs do notphase reverse when the valid input signal range is exceeded. Onthe ADCMP607, latch and programmable hysteresis features arealso provided with a unique single-pin control option.The ADCMP606 is available in a 6-lead SC70 package and theADCMP607 is available in a 12-lead LFCSP package.Applications High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)

Digital to Analog Converters - DAC CMOS CONVERTER IC

RF Amplifier Low Noise Amplifier, LNA

The HMC407MS8G & HMC407MS8GE are high?efficiency GaAs InGaP Heterojunction Bipolar?Transistor (HBT) MMIC Power amplifiers which?operate between 5 and 7 GHz. The amplifier requires?no external matching to achieve operation and is?thus truly 50 Ohm matched at input and output. The?amplifier is packaged in a low cost, surface mount?8 leaded package with an exposed base for improved?RF and thermal performance. The amplifier?provides 15 dB of gain, +29 dBm of saturated power?at 28% PAE from a +5V supply voltage. Power down?capability is available to conserve current consumption?when the amplifier is not in use.Applications UNII HiperLAN

The HMC415LP3(E) is a high efficiency GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC Power amplifier which operates between 4.9 and 5.9 GHz. The amplifier is packaged in a low cost, leadless surface mount package with an exposed base for improved RF and thermal performance. With a minimum of external components, the amplifier provides 20 dB of gain, +26 dBm of saturated power, and 34% PAE from a +3V supply voltage. Vpd can be used for full power down or RF output power/current control. For +15 dBm OFDM output power (64 QAM, 54 Mbps), the HMC415LP3(E) achieves an error vector magnitude (EVM) of 3.7% meeting 802.11a linearity requirements.Applications 802.11a WLAN HiperLAN WLAN Access Points UNII & ISM Radios

The HMC384LP4(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO with integrated resonator, negative resistance device, varactor diode, and buffer amplifier. The VCO?s phase noise performance is excellent over temperature, shock, vibration and process due to the oscillator?s monolithic structure. Power output is 3.5 dBm typical from a 3V supply voltage. The voltage controlled oscillator is packaged in a low cost leadless QFN 4x4 mm surface mount package.APPLICATIONS Wireless Infrastructure Industrial Controls Test Equipment Military

The HMC390LP4(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO with integrated resonator, negative resistance device, varactor diode, and buffer amplifier. Covering 3.55 to 3.9 GHz, the VCO?s phase noise performance is excellent over temperature, shock, vibration and process due to the oscillator?s monolithic structure. Power output is 4.7 dBm typical from a single supply of 3V @ 42 mA. The voltage controlled oscillator is packaged in a low cost leadless QFN 4?4 mm surface mount package.APPLICATIONS Wireless Local Loop (WLL) VSAT & Microwave Radio Test Equipment & Industrial Controls Military