The LTC1628/LTC1628-PG are high performance dual step-down switching regulator controllers that drive all N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows adjustment of the frequency up to 300kHz. Power loss and noise due to the ESR of the input capacitors are minimized by operating the two controller output stages out of phase.OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The precision 0.8V reference and power good output indicator are compatible with future microprocessor generations, and a wide 3.5V to 30V (36V maximum) input supply range encompasses all battery chemistries.A RUN/SS pin for each controller provides both soft-start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipation during short-circuit conditions when overcurrent latchoff is disabled. Output overvoltage protection circuitry latches on the bottom MOSFET until VOUT returns to normal. The FCB mode pin can select among Burst Mode, constant frequency mode and continuous inductor current mode or regulate a secondary winding. The LTC1628-PG includes a power good output pin that replaces the FLTCPL, fault coupling control pin of the LTC1628.Applications Notebook and Palmtop Computers, PDAs Battery Chargers Portable Instruments Battery-Operated Digital Devices DC Power Distribution Systems

DC551A-A: Demo Board for LTC4002-4.2 Standalone Li-Ion Switch Mode Battery Charger.

DC562A-A: Demo Board for the LT1725 General Purpose Isolated Flyback Controller.

DC562A-C: Demo Board for the LT1725 General Purpose Isolated Flyback Controller.

DC579A: Demo Board for LTC2600 Octal 16-Bit Rail-to-Rail DACs in 16-Lead SSOP.

DC690A: Demo Board for the LT3420 Photoflash Capacitor Chargers with Automatic Refresh.

DC711A-A: Demo Board for the LT3468 Photoflash Capacitor Chargers in ThinSOT.

The ADCA5190 is a medium power gain block amplifier that provides excellent linearity across a flexible bias range allowing power efficient design implementation for various applications. The device provides 19.1 dB of flat gain up to 1800 MHz, making this ideal for Data Over Cable Service Interface Specification (DOCSIS?) 4.0 downstream applications. The device is also well suited for upstream applications to 700 MHz as the output stage. The device is conveniently packaged in an industry-standard, 32-lead, 5 mm ? 5 mm lead frame chip-scale package (LFCSP) with an exposed pad on the bottom of the package for improved thermal performance.APPLICATIONS 45 MHz to 1800 MHz CATV infrastructure amplifier systems 5 MHz to 700 MHz upstream Remote physical layer (PHY) DOCSIS 3.1 and DOCSIS 4.0 compliant

The ADCA5191 is a medium power gain block amplifier that provides excellent linearity across a flexible bias range allowing power efficient design implementation for various applications.The device provides 25.8 dB of flat gain up to 1800 MHz, making this ideal for Data Over Cable Service Interface Specification (DOCSIS) 4.0 downstream applications. The device is also well suited for upstream applications to 700 MHz as the output stage. It is conveniently packaged in an industry-standard, 5 mm ? 5 mm, 32-lead, lead frame chip-scale package (LFCSP) with an exposed pad on the bottom of the package for improved thermal performance.APPLICATIONS45 MHz to 1800 MHz CATV infrastructure amplifier systems5 MHz to 700 MHz upstreamRemote physical layer (PHY)DOCSIS? 3.1 and DOCSIS 4.0 compliant

The ADCLK905 (one input, one output), ADCLK907 (dual oneinput, one output), and ADCLK925 (one input, two outputs) areultrafast clock/data buffers fabricated on the Analog Devices, Inc.,proprietary XFCB3 silicon germanium (SiGe) bipolar process.The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).The inputs have center tapped, 100 ?, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.Applications Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking