The ADP7102 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 ?F ceramic output capacitor. The ADP7102 is available in seven fixed output voltage options and an adjustable version, which allows output voltages that range from 1.22 V to VIN ? VDO via an external feedback divider. The ADP7102 output noise voltage is 15 ?V rms and is independent of the output voltage. A digital power good output allows power system monitors to check the health of the output voltage. A user programmable precision undervoltage lockout function facilitates sequencing of multiple power supplies. The ADP7102 is available in 8-lead, 3 mm ? 3 mm LFCSP and 8-lead SOIC packages. The LFCSP offers a very compact solution and also provides excellent thermal performance for applications requiring up to 300 mA of output current in a small, low-profile footprint. APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation

The ADP7142 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 40 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed signal circuits operating from 39 V down to 1.2 V rails. Using an advanced proprietary architecture, the device provides high power supply rejection, low noise, and achieves excellent line and load transient response with a small 2.2 ?F ceramic output capacitor. The ADP7142 regulator output noise is 11 ?V rms independent of the output voltage for the fixed options of 5 V or less.The ADP7142 is available in 15 fixed output voltage options. The following voltages are available from stock: 1.2 V (adjustable), 1.8 V, 2.5 V, 3.3 V, 3.8 V, and 5.0 V. Additional voltages available by special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.0 V, 4.2 V, and 4.6 V.Each fixed output voltage can be adjusted above the initial set point with an external feedback divider. This allows the ADP7142 to provide an output voltage from 1.2 V to VIN ? VDO with high PSRR and low noise.User programmable soft start with an external capacitor is available in the LFCSP and SOIC packages.The ADP7142 is available in a 6-lead, 2 mm ? 2 mm LFCSP making it not only a very compact solution, but it also provides excellent thermal performance for applications requiring up to 200 mA of output current in a small, low profile footprint. The ADP7142 is also available in a 5-lead TSOT and an 8-lead SOIC.APPLICATIONS Regulation to noise sensitive applications ADC, DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation Automotive

The ADP7142 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 40 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed signal circuits operating from 39 V down to 1.2 V rails. Using an advanced proprietary architecture, the device provides high power supply rejection, low noise, and achieves excellent line and load transient response with a small 2.2 ?F ceramic output capacitor. The ADP7142 regulator output noise is 11 ?V rms independent of the output voltage for the fixed options of 5 V or less.The ADP7142 is available in 15 fixed output voltage options. The following voltages are available from stock: 1.2 V (adjustable), 1.8 V, 2.5 V, 3.3 V, 3.8 V, and 5.0 V. Additional voltages available by special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.0 V, 4.2 V, and 4.6 V.Each fixed output voltage can be adjusted above the initial set point with an external feedback divider. This allows the ADP7142 to provide an output voltage from 1.2 V to VIN ? VDO with high PSRR and low noise.User programmable soft start with an external capacitor is available in the LFCSP and SOIC packages.The ADP7142 is available in a 6-lead, 2 mm ? 2 mm LFCSP making it not only a very compact solution, but it also provides excellent thermal performance for applications requiring up to 200 mA of output current in a small, low profile footprint. The ADP7142 is also available in a 5-lead TSOT and an 8-lead SOIC.APPLICATIONS Regulation to noise sensitive applications ADC, DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation Automotive

The ADP7159 is an adjustable linear regulator that operates from 2.3 V to 5.5 V and provides up to 2 A of output current. Output voltages from 1.2 V to 3.3 V are possible depending on the model. Using an advanced proprietary architecture, the device provides high power supply rejection and ultralow noise, achieving excellentline and load transient response with only a 10 ?F ceramicoutput capacitor.The ADP7159 is available in four models that optimize powerdissipation and PSRR performance as a function of the inputand output voltage. The typical output noise of the ADP7159 regulator is 0.9 ?V rmsfrom 100 Hz to 100 kHz and 1.7 nV/?Hz for noise spectral densityfrom 10 kHz to 1 MHz. The ADP7159 is available in 10-lead,3 mm ? 3 mm LFCSP and 8-lead SOIC packages, making it notonly a very compact solution, but also providing excellent thermal performance for applications requiring up to 2 A of outputcurrent in a small, low profile footprint.Applications Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs Communications and infrastructure Backhaul and microwave links

The ADP7185 is a complementary metal oxide semiconductor(CMOS), low dropout (LDO) linear regulator that operatesfrom ?2.0 V to ?5.5 V and provides up to ?500 mA of output current. This high output current LDO is ideal for regulation of high performance analog and mixed signal circuits operatingfrom ?0.5 V down to ?4.5 V. Using an advanced proprietaryarchitecture, the ADP7185 provides high power supple rejectionratio (PSRR) and low noise, and it achieves excellent line and loadtransient response with a small 4.7 ?F ceramic output capacitor.The ADP7185 is available in 15 fixed output voltage options.The following voltages are available from stock: ?0.5 V, ?1.0 V,?1.2 V, ?1.5 V, ?1.8 V, ?2.0 V, ?2.5 V, ?3.0 V, and ?3.3 V.Additional voltages available by special order are ?0.8 V, ?0.9 V, ?1.3 V, ?2.8 V, ?4.2 V, and ?4.5 V. An adjustable version is also available which allows output voltages that range from ?0.5 V to ?VIN + 0.5 V with an external feedback divider.The enable logic feature is capable of interfacing with positive or negative logic levels for maximum flexibility.The ADP7185 regulator output noise is 4 ?V rms independent of the output voltage. The ADP7185 is available in an 8-lead, 2 mm ? 2 mm LFCSP, making it not only a very compact solution but also providing excellent thermal performance for applications requiring up to ?500 mA of output current in a small, low profile footprint.Applications Regulation to noise sensitive applications: analog-to-digital converters (ADCs), digital-to-analog converters (DACs), precision amplifiers Communications and infrastructure Medical and healthcare Industrial and instrumentation

The ADRF5044 is a general-purpose, single-pole, four-throw (SP4T) switch manufactured using a silicon process. It comes in a 24-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 100 MHz to 30 GHz.This broadband switch requires dual-supply voltages, +3.3 V and ?3.3 V, and provides complementary metal-oxide semiconductor (CMOS)/low voltage transistor-transistor logic (LVTTL) logic-compatible control.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems

The ADRF5549 is a dual-channel, integrated, RF front-end multichip module designed for time division duplexing (TDD) applications that operates from 1.8 GHz to 2.8 GHz. The ADRF5549 is configured in dual channels with a cascading, two-stage, low noise amplifier (LNA) and a high power, silicon single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.4 dB and a high gain of 35 dB with an output third-order intercept point (OIP3) of 32 dBm typical.In low gain mode, one stage of the two-stage LNA is in bypass mode providing 17 dB of gain at a lower current of 35 mA. In power-down mode, the LNAs are turned off, and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.6 dB and handles a long-term evolution (LTE) full lifetime average (9 dB peak to average ratio (PAR)) of 40 dBm and 43 dBm for a 9 dB PAR LTE single event (ApplicationsWireless InfrastructureTDD massive multiple input and multiple output (MIMO) and active antenna systemsTDD-based communication systems

The ADRF6821 is a highly integrated, dual radio frequency (RF) input, zero intermediate frequency (IF)/low IF RFIC receiverwith a quadrature demodulator, digital step attenuator (DSA),IF linear amplifiers, an integrated, fractional-N phase-locked loop (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication digital predistortion (DPD) systems.The high isolation 2:1 RF switch and on-chip wideband RFbalun enable the ADRF6821 to support two single-ended, 50 ? terminated RF inputs. A programmable attenuator ensures anoptimal differential RF input level to the high linearity demodulatorcore. The integrated attenuator offers an attenuation range of 15 dB with a step size of 1 dB. High linearity IF amplifiers follow the demodulator and provide an interface to the next componentin the chain, typically an analog-to-digital converter (ADC).The ADRF6821 offers two alternatives for generating thedifferential local oscillator (LO) input signal: internally viathe on-chip fractional-N synthesizer with low phase noiseVCOs or externally via a low phase noise LO signal. Theintegrated synthesizer enables continuous LO coverage from 450 MHz to 2800 MHz. The PLL reference input supports awide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).When selected, the output of the internal fractional-N synthesizeris applied to a divide by 2, quadrature phase splitter. From theexternal LO path, a 2? LO signal can be used with the divide by 2,quadrature phase splitter to generate the quadrature LO inputs to the mixers.The ADRF6821 is fabricated using an advanced silicon germanium(SiGe), bipolar complementary metal oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS compliant,8 mm ? 8 mm LFCSP package with an exposed pad. Performanceis specified over the ?40?C to +105?C case temperature range.Applications Cellular W-CDMA/GSM/LTE DPD receivers? Microwave, point to point radios

The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual channel transmitters, observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 2G, 3G and 4G macro-cell base stations, and active antenna, applications.The transmitters use an innovative direct conversion modulator that achieves multi-carrier macro-base-station quality performance and very low power. In 3G/4G mode, the maximum large-signal bandwidth is 200MHz. In MC-GSM mode, which has higher in-band SFDR, the maximum large-signal bandwidth is 75MHz.The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated. The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer is used to generate the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All VCO and loop filter components are integrated.The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode. The core of the ADRV9008-2 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

The ADV3205 is a fully buffered crosspoint switch matrix that operates on ?5 V, making it ideal for video applications. It offers a ?3 dB signal bandwidth of 60 MHz and channel switch times of less than 60 ns with 0.1% settling. The ADV3205 has excellent crosstalk performance, and ground/power pins surround all inputs and outputs to provide extra shielding required for the most demanding applications. The differential gain and differential phase of better than 0.1% and 0.1?, respectively, along with 0.1 dB flatness out to 10 MHz, make the ADV3205 an excellent choice for many video applications.The ADV3205 includes 16 independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs. The ADV3205 has a gain of +2 and operates on voltage supplies of ?5 V while consuming only 34 mA of current. Channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array.?The ADV3205 is packaged in a 100-lead LQFP and is available over the commercial temperature range of 0?C to 70?C.?ApplicationsCCTV surveillanceVideo routers (NTSC, PAL, S-Video, SECAM)Video conferencing