The HMC778LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an integrated Voltage Controlled Oscillator (VCO). The input reference frequency range is DC to 350 MHz while the advanced delta-sigma modulator design in the fractional synthesizer allows both ultra-fine step sizes and very low spurious products. The highly integrated structure provides excellent phase noise performance over temperature, shock and process. In addition, the HMC778LP6CE offers frequency sweep and modulation features, external triggering, double-buffering, exact frequency control, phase modulation and more. The HMC778LP6CE is packaged in a leadless QFN 6 x 6 mm surface mount package.For theory of operation and register map refer to the 'PLLs w/ Integrated VCO - Microwave VCOs' Operating Guide.Applications VSAT Radio Microwave Point-To-Point Radios Test Equipment & Industrial Control Military End-Use Phased Array Applications FMCW Radar Systems

The HMC960LP4E is a digitally programmable dual channel variable gain amplifier. It supports discrete gain steps from 0 to 40 dB in precise 0.5 dB steps. It features a glitch free architecture to provide exceptionally smooth gain transitions. The device has matched gain paths which provide excellent quadrature balance over a wide signal bandwidth.The HMC960LP4E provides an SPI programmable input impedance of 100? differential or 400? differential (default).Externally controlled common mode output feature enables the HMC960LP4E to provide a flexible output interface to other parts in the signal path. Gain can be controlled via either a parallel interface (GC[6:0]) or via the read/write serial port (SPI).Housed in a compact 4x4mm (LP4) SMT QFN package, the HMC960LP4E requires minimal external components and provides a low cost alternative to more complicated switched amplifier architectures.Applications Baseband I/Q Transceivers Direct Conversion &?Low IF Transceivers Diversity Receivers ADC Drivers Adaptive Gain Control

The HMC1010LP4E Power Detector is designed for RF power measurement, and control applications for frequencies up to 3.9 GHz. The detector provides an accurate RMS representation of any RF/IF input signal. The output is a temperature compensated monotonic, representation of real signal power, measured with an input sensing range of 60 dB.The HMC1010LP4E is ideally suited to those wide bandwidth, wide dynamic range applications, requiring repeatable measurement of real signal power, especially where RF/IF wave shape and/or crest factor change with time.The integration bandwidth of the HMC1010LP4E is digitally programmable with the use of input pins SC I1- 4 with a range of more than 4 decades. This allows the user to dynamically set the operation bandwidth providing the capability of handling different types of modulations on the same platform.The HMC1010LP4E features an internal op-amp at output stage, which provides for slope & intercept adjustments and enables controller application.Applications Log ?> Root-Mean-Square?(RMS) Conversion Received Signal Strength?Indication (RSSI) Transmitter Signal Strength?Indication (TSSI) RF Power Amplifier Efficiency Control Receiver Automatic Gain Control Transmitter Power Control

The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages.The AD633 is laser calibrated to a guaranteed total accuracy of 2% of full scale. Nonlinearity for the Y input is typically less than 0.1% and noise referred to the output is typically less than 100 ?V rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/?s slew rate, and the ability to drive capacitive loads make the AD633 useful in a wide variety of applications where simplicity and cost are key concerns.The versatility of the AD633 is not compromised by its simplicity. The Z input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications.The AD633 is available in 8-lead PDIP and SOIC packages. It is specified to operate over the 0?C to 70?C commercial temperature range (J Grade) or the ?40?C to +85?C industrial temperature range (A Grade).Product Highlights The AD633 is a complete four-quadrant multiplier offered in low cost 8-lead SOIC and PDIP packages. The result is a product that is cost effective and easy to apply. No external components or expensive user calibration are required to apply the AD633. Monolithic construction and laser calibration make the device stable and reliable. High (10 M?) input resistances make signal source loading negligible. Power supply voltages can range from ?8 V to ?18 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive.Applications Multiplication, division, squaring Modulation/demodulation, phase detection Voltage-controlled amplifiers/attenuators/filters

The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC core output is connected internally to a noise shaping requantizer (NSR) block. The device supports two output modes that are selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6672 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block is programmed to provide a bandwidth of up to 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6672 can achieve up to 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 11 bits. The AD6672 can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios

The AD8349 is high performance quadrature modulator design for use as a single stage up-converter within wireless infrastructure equipment.The AD8349 provides a high output power and very low noise floor supporting a significant improvement in the output signal range. Additionally the excellent phase and amplitude balance accuracy support a higher sideband suppression specification enabling higher order / capacity QAM modulated radios.The AD8349 has been tested for use over the common Cellular bands (900 MHz, 1.9 GHz, 2.1 GHz) meeting the needs as specified by the CDMA/GSM Edge/W-CDMA standards.The AD8349 is supplied in 16-lead Thin Shrunk Small Outline (TSSOP) package, and fully specified over -40?C to 85?C temperature range.APPLICATIONS Cellular/PCS communication systems infrastructure WCDMA/CDMA2000/PCS/GSM/EDGE Wireless LAN/wireless local loop LMDS/broadband wireless access systemsAVAILABILITYSamples (part number AD8349ARE) and an evaluation board (part number AD8349-EVAL) are available. Other Modulator / Demodulator ProductsAD8345 - 250 - 1000 MHz RF / IF Quadrature ModulatorAD8346 - 2.5 GHz Direct Conversion Quadrature ModulatorAD8347 - 800 MHz to 2.7 GHz RF / IF Quadrature DemodulatorAD8348 - 50 - 1000 MHz RF / IF Quadrature Demodulator

The AD8432 is a dual-channel, low power, ultralow noiseamplifier with selectable gain and active impedance matching.Each channel has a single-ended input, differential output, andintegrated input clamps. By pin strapping the gain setting pins, four accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (?4, ?8, ?12, and ?16, respectively) are possible. A bandwidth of200 MHz at G = 12.04 dB makes this amplifier well suited for many high speed applications.The exceptional noise performance of the AD8432 is madepossible by the active impedance matching. Using a feedback network, the input impedance of the amplifiers can be adjusted to match the signal source impedance without compromising the noise performance. Impedance matching and low noise in the AD8432 allow designers to create wider dynamic rangesystems that are able to detect even very low level signals. The AD8432 achieves 0.85 nV/?Hz input-referred voltage noise fora gain of 12.04 dB. The AD8432?s ultralow noise, low distortion, gain accuracy, and channel-to-channel matching are ideal for high performance ultrasound systems and for processing I/Qdemodulator signals.The AD8432 operates on a single supply of 5 V at 24 mA. It isavailable in a 4 mm ? 4 mm, 24-lead LFSCP. The LFCSP featuresan exposed paddle that provides a low thermal resistance path to the PCB, which enables more efficient heat transfer and increasesreliability. The operating temperature range is ?40?C to +85?C.Applications CW Doppler ultrasound front ends? Low noise preamplification? Predriver for I/Q demodulators and phase shifters? Wideband analog-to-digital drivers

The AD5424?/?AD5433?/ AD5445 are CMOS 8-, 10-, and 12-bitcurrent output digital-to-analog converters (DACs), respectively.These devices operate from a 2.5 V to 5.5 V power supply,making them suitable for battery-powered applications andmany other applications. These DACs utilize data readback,allowing the user to read the contents of the DAC register viathe DB pins. On power-up, the internal register and latches arefilled with 0s and the DAC outputs are at zero scale.As a result of manufacturing with a CMOS submicron process,they offer excellent 4-quadrant multiplication characteristics,with large signal multiplying bandwidths of up to 10 MHz.The applied external reference input voltage (VREF) determines thefull-scale output current. An integrated feedback resistor (RFB)provides temperature tracking and full-scale voltage outputwhen combined with an external I-to-V precision amplifier.While these devices are upgrades of the AD5424 / AD5433 /AD5445 in multiplying bandwidth performance, they have alatched interface and cannot be used in transparent mode.The AD5424 is available in a small, 20-lead LFCSP and a small,16-lead TSSOP, while the AD5433 and AD5445 DACs are availablein a small, 20-lead LFCSP and a small, 20-lead TSSOP.The EVAL-AD5445SDZ evaluation board is available forevaluating DAC performance. For more information, see theUG-333 evaluation board user guide.APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming

The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.The conversion process and data acquisition are controlled using ASYNC and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of ASYNC and conversion is also initiated at this point. There are no pipeline delays associated with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V to VREFA input or a 0 V to 2 ? VREFA with either straight binary or twos complement output coding. The conversion time is determined by the ASCLK frequency because it is also used as the master clock to control the conversion.The DAC section of the AD5590 comprises sixteen 12-bit DACs divided into two groups of eight. Each group has an on-chip reference. The on-board references are off at power-up, allowing the use of external references. The internal references are enabled via a software write.The AD5590 incorporates a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain powered up at this level until a valid write takes place. The DAC contains a power-down feature that reduces the current consumption of the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a user-programmable code: zero scale, midscale, or full scale.The AD5590 contains eight low noise, single-supply amplifiers. These amplifiers can be used for signal conditioning for the ADCs, DACs, or other independent circuitry, if required.APPLICATIONS Optical Line Cards (Monitoring and Control) Base Stations General Purpose Analog I/O Monitoring and control

The AD5668 device is a low power, octal, 16-bit, buffered voltage-output DAC. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The AD5668 and AD5628 are available inboth a 4 mm ? 4 mm LFCSP and a 16-lead TSSOP, while theAD5648 is available in both a 14-lead and 16-lead TSSOP.The AD5628/AD5648/AD5668 have an on-chip reference withan internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 havea 1.25 V 5 ppm/?C reference, giving a full-scale output rangeof 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 havea 2.5 V 5 ppm/?C reference, giving a full-scale output range of5 V. The on-board reference is off at power-up, allowing the useof an external reference. The internal reference is enabled via asoftware write.The part incorporates a power-on reset circuit that ensures that theDAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1,AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) andremains powered up at this level until a valid write takes place.The part contains a power-down feature that reduces the currentconsumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or allDAC channels. The outputs of all DACs can be updated simultaneouslyusing the LDAC function, with the added functionalityof user-selectable DAC channels to simultaneously update. Thereis also an asynchronous CLR that updates all DACs to a userprogrammablecode?zero scale, midscale, or full scale.The AD5628/AD5648/AD5668 utilize a versatile 3-wire serialinterface that operates at clock rates of up to 50 MHz and iscompatible with standard SPI?, QSPI?, MICROWIRE?, andDSP interface standards. The on-chip precision output amplifierenables rail-to-rail output swing.Product Highlights Octal, 12-/14-/16-bit DAC. On-chip 1.25 V/2.5 V, 5 ppm/?C reference. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP. Power-on reset to 0 V or midscale. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Applications Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators