The ADRF6821 is a highly integrated, dual radio frequency (RF) input, zero intermediate frequency (IF)/low IF RFIC receiverwith a quadrature demodulator, digital step attenuator (DSA),IF linear amplifiers, an integrated, fractional-N phase-locked loop (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication digital predistortion (DPD) systems.The high isolation 2:1 RF switch and on-chip wideband RFbalun enable the ADRF6821 to support two single-ended, 50 ? terminated RF inputs. A programmable attenuator ensures anoptimal differential RF input level to the high linearity demodulatorcore. The integrated attenuator offers an attenuation range of 15 dB with a step size of 1 dB. High linearity IF amplifiers follow the demodulator and provide an interface to the next componentin the chain, typically an analog-to-digital converter (ADC).The ADRF6821 offers two alternatives for generating thedifferential local oscillator (LO) input signal: internally viathe on-chip fractional-N synthesizer with low phase noiseVCOs or externally via a low phase noise LO signal. Theintegrated synthesizer enables continuous LO coverage from 450 MHz to 2800 MHz. The PLL reference input supports awide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).When selected, the output of the internal fractional-N synthesizeris applied to a divide by 2, quadrature phase splitter. From theexternal LO path, a 2? LO signal can be used with the divide by 2,quadrature phase splitter to generate the quadrature LO inputs to the mixers.The ADRF6821 is fabricated using an advanced silicon germanium(SiGe), bipolar complementary metal oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS compliant,8 mm ? 8 mm LFCSP package with an exposed pad. Performanceis specified over the ?40?C to +105?C case temperature range.Applications Cellular W-CDMA/GSM/LTE DPD receivers? Microwave, point to point radios

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADV3205 is a fully buffered crosspoint switch matrix that operates on ?5 V, making it ideal for video applications. It offers a ?3 dB signal bandwidth of 60 MHz and channel switch times of less than 60 ns with 0.1% settling. The ADV3205 has excellent crosstalk performance, and ground/power pins surround all inputs and outputs to provide extra shielding required for the most demanding applications. The differential gain and differential phase of better than 0.1% and 0.1?, respectively, along with 0.1 dB flatness out to 10 MHz, make the ADV3205 an excellent choice for many video applications.The ADV3205 includes 16 independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs. The ADV3205 has a gain of +2 and operates on voltage supplies of ?5 V while consuming only 34 mA of current. Channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array.?The ADV3205 is packaged in a 100-lead LQFP and is available over the commercial temperature range of 0?C to 70?C.?ApplicationsCCTV surveillanceVideo routers (NTSC, PAL, S-Video, SECAM)Video conferencing

The ADV3219 and ADV3220 are high speed, high slew rate,buffered, 2:1 analog multiplexers. They offer a ?3 dB signalbandwidth greater than 800 MHz and channel switch times ofless than 20 ns with 1% settling. With ?82 dB of crosstalk and?88 dB isolation (at 5 MHz), the ADV3219 and ADV3220 areuseful in many high speed applications. The differential gain ofless than 0.02% and the differential phase of less than 0.02?,together with 0.1 dB flatness beyond 100 MHz while driving a75 ? back terminated load, make the ADV3219 and ADV3220ideal for all types of signal switching. The ADV3219/ADV3220 include an output buffer that can beplaced into a high impedance state to allow multiple outputs tobe connected together for cascading stages without the off channelsloading the output bus. The ADV3219 has a gain of +1, and theADV3220 has a gain of +2; they both operate on ?5 V supplieswhile consuming less than 7.5 mA of idle current.The ADV3219/ADV3220 are available in the 8-lead LFCSPpackage over the extended industrial temperature range of?40?C to +85?C. Applications Routing of high speed signals including ??Video (NTSC, PAL, S, SECAM, YUV, and RGB) ??Compressed video (MPEG, wavelet) ??3-level digital video (HDB3) Data communications Telecommunications

The ADV3226/ADV3227 are high speed 16 ? 16 analog crosspoint switch matrices. They offer a ?3 dB signal bandwidth greater than 750 MHz and channel switch times of less than 20 ns with 1% settling.The ADV3226/ADV3227 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3226 has a gain of +1 and the ADV3227 has a gain of +2. They both operate on voltage supplies of ?5 V while consuming only 118 mA (ADV3226) and 133 mA (ADV3227) of idle current. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3226/ADV3227 are available in the 100-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? Compressed video (MPEG, wavelet) ? ? 3-level digital video (HDB3) Data communications Telecommunications

The ADV3228/ADV3229 are high speed 8 ? 8 analog crosspoint switch matrices. They offer a ?3 dB large signal bandwidth of 750 MHz (ADV3228) and a slew rate of 2500 V/?s.The ADV3228/ADV3229 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3228 has a gain of +1, the ADV3229 has a gain of +2, and they both operate on voltage supplies of ?5 V. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array.The ADV3228/ADV3229 are available in the 72-lead LFCSP package over the extended industrial temperature range of ?40?C to +85?C.Applications Routing of high speed signals including: ? ? ? Video (NTSC, PAL, S, SECAM, YUV, RGB) ? ? ? Compressed video (MPEG, wavelet) ? ? ? 3-level digital video (HDB3) Data communications Telecommunications

The ADXL213 is a low cost, low power, complete dual axis accelerometer with signal conditioned, duty cycle modulated outputs, all on a single monolithic IC. The ADXL213 measures acceleration with a full-scale range of ?1.2 g (typical). The ADXL213 can measure both dynamic acceleration (e.g., vibration) and static acceleration (e.g., gravity).The outputs are digital signals whose duty cycles (ratio of pulse width to period) are proportional to acceleration (30%/g). The duty cycle outputs can be directly measured by a microcontroller without an A/D converter or glue logic.Innovative design techniques are used to ensure high zero g bias stability (typically better than 0.25 mg/?C), as well as tight sensitivity stability (typically better than 50 ppm/?C).The typical noise floor is 160 ?g/?, allowing signals below 1 mg (0.06? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (The user selects the bandwidth of the accelerometer usingcapacitors CX and CYM at the XFILT and YFILT pins. Bandwidths of0.5 Hz to 250 Hz may be selected to suit the application.The ADXL213 is available in a 5mm x 5mm x 2mm, 8-pad hermetic LCC package.ApplicationsAutomotive tilt alarmData projectorsNavigationPlatform stabilization/levelingAlarms and motion detectorsHigh accuracy, 2-axis tilt sensing

The LT1182/LT1183 are dual current mode switching regulators that provide the control function for Cold Cathode Fluorescent Lighting (CCFL) and Liquid Crystal Display (LCD) Contrast. The LT1184/LT1184F provide only the CCFL function. The ICs include high current, high efficiency switches, an oscillator, a reference, output drive logic, control blocks and protection circuitry. The LT1182 permits positive or negative voltage LCD contrast operation. The LT1183 permits unipolar contrast operation and pins out an internal reference. The LT1182/LT1183 support grounded and floating lamp configurations. The LT1184F supports grounded and floating lamp configurations. The LT1184 supports only grounded lamp configurations.Applications Notebook and Palmtop Computers Portable Instruments Automotive Displays Retail Terminals

The LTC2492 is a 4-channel (2-channel differential), 24-bit, No Latency ??? ADC with Easy Drive technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2492 includes a high accuracy temperature sensor and an integrated oscillator. This device can be configured to measure an external signal (from combinations of 4 analog input channels operating in single-ended or differential modes) or its internal temperature sensor. It can be programmed to reject line frequencies of 50Hz, 60Hz, or simultaneous 50Hz/60Hz and configured to double its output rate. The integrated temperature sensor offers 1/30th?C resolution and 2?C absolute accuracy. The LTC2492 allows a wide common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion after a new channel selection is valid.Applications Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control