WEBENCH BARE BD BRDG IA

High Efficiency Boost Switching Controller Eval Board with 12 Volt Output

MSP430 868/915MHZ Wireless Target Board

TPS82693 800-mA, High-Efficiency MicroSiP(tm) Step-Down Converter Evaluation Module Board

Broadening the largest portfolio of low drop-out regulators (LDOs), TI introduces a new family of AEC-Q100-qualified high-voltage LDOs for automotive and industrial applications. With ultra-low quiescent current and the ability to support an input voltage up to 60-V, the LDOs  support many applications that connect directly to a car or truck battery, such as cluster, door modules, power steering, infotainment systems and lighting controls.

Key features and benefits of the LDO family for direct connection to the car battery:

• Ultra-low quiescent current as low as 10 uA: Lowest quiescent current in standby mode means lower power consumption and increased battery endurance time.
• Internal ESR compensation offers the flexibility to use a wide range of output capacitors, including ceramic: Flexibility allows the customer to choose from a wide range of output ceramic capacitors to reduce system cost and increase stability.
• High-input voltage allows designers to connect direct to the car battery: Up to 40-V Vin for normal operation and 45-V transient (TPS7A16xx-Q1 can support up to 60-V normal operation for trucks and heavy-duty equipment)
• Tracking function provides close to zero tolerance between on-board and off-board power supplies: Tracking helps customers get more accurate data from the off-board sensors..
• Integrated window watchdog: enables higher functional safety to be designed into end equipments.

LM3447 Flyback Controller for LED Lighting Evaluation Module Board

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

Ethernet Development Tools 5-Port 10/100 Ethernet Switch

Ethernet Development Tools 5-Port 10/100 Ethernet Switch

Ethernet Development Tools 5-Port 10/100 Ethernet Switch