The ADM1186-1 and ADM1186-2 are integrated, four-channel, voltage monitoring and sequencing devices. A 2.7 V to 5.5 V power supply is required on the VCC pin for power.Four precision comparators monitor four voltage rails, with all comparators sharing a 0.6 V reference and a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the Under Voltage (UV) trip points for the monitored supply rails.The ADM1186-1 and ADM1186-2 have four open drain enable outputs, OUTx, that are used to enable power supplies. An open drain power good output, PWRGD, is provided that indicatesthe four VINx inputs are above their UV thresholds.A state machine monitors the state of the UP and?DOWN pins on the ADM1186-1 or the UP/overbar: DOWN pin on the ADM1186-2 to control the supply sequencing direction. In the ?Wait Start?state, a rising edge transition on the UP or UP/DOWN pin triggers a power-up sequence. A falling edge transition on the DOWN or UP/DOWN pin in the ?Power Up Done? statetriggers a power down sequence.During a power up sequence, the state machine enables each power supply in turn. The supply output voltage is monitored to determine if it rises above the UV threshold level within a userdefined duration called the blanking time. If a supply rises above the UV threshold then the next enable output in the sequence is turned on. In addition to the blanking time a user may also define sequencing time delays between each enable output turning on. When all four enable outputs are on, and the four VINx pins are above their UV trip points the power up sequence is complete. The ADM1186-1 provides an open drain pin, SEQ_DONE, that is asserted high to provide an indication that an up sequence is complete. The SEQ_DONE pins is allows multiple cascadedADM1186-1 devices to be perform controlled power up and down sequences. During a power down sequence the enable outputs turn off inreverse order. The sequence time delays between successive supplies the same as during the power up sequence, and no blanking time is used during a power down sequence. At the end of a down sequence the SEQ_DONE pin is brought low. During sequencing and when powered up, the state machine continuously monitors for any fault conditions. Faults include a UV condition on any of the inputs, or an unexpected controlinput. Any fault that occurs causes the state machine to enter a fault handler. This immediately turns off all enable outputs, and ensures that the device is ready to start a new up sequence. The ADM1186-1 has a bi-directional open drain pin, FAULT, that facilitates fault handling when using multiple devices. An ADM1186-1 experiencing a fault condition drives the FAULT pin low, causing other connected ADM1186-1devices to enter their own fault handling state.The ADM1186-1 is available in a 20-lead QSOP package andthe ADM1186-2 is available in a 16-lead QSOP package.

The ADM1192 is an integrated current sense amplifier that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (ADC), communicated through an I2C interface.An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC pin and the SENSE pin.A 12-bit ADC can measure the current seen in the sense resistor and in the supply voltage on the VCC pin. An industry-standard I2C interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by an I2C command. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever it is required. Up to four unique I2C addresses can be created, depending on the way the ADR pin is connected.A SETV pin is also included. A voltage applied to this pin is internally compared to the output voltage on the current sense amplifier. The output of the SETV comparator asserts when the current sense amplifier output exceeds the SETV voltage. This event is detected at the ALERT block. The ALERT block then charges up the external TIMER capacitor with a fixed current. When this timing cycle is complete, the ALERT output asserts.The ALERT output can be used as a flag to warn a micro-controller or field programmable gate array (FPGA) of an overcurrent condition. ALERT outputs of multiple ADM1192 devices can be tied together and used as a combined alert.A basic P-channel FET hot swap circuit can be implemented with the ALERT output. The value of the TIMER capacitor should be set so that the charging time of this capacitor is much longer than the period where a higher than nominal inrush current may be flowing.The ADM1192 is packaged in a 10-lead MSOP.APPLICATIONS Power monitoring/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers

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