The?AD7794/AD7795 are low power, low noise, complete analog front ends for high precision measurement applications. They contain a low noise, 24-/16-bit ?-? ADC with six differential inputs. The on-chip low noi se instrumentation amplifier means that signals of small amplitude can be interfaced directly to the ADC.Each device contains a precision, low noise, low drift internal band gap reference, and can also accept up to two external differential references. Other on-chip features include programmable excitation current sources, burnout currents, and a bias voltage generator that is used to set the common-mode voltage of a channel to AVDD/2. The low-side power switch can be used to power down bridge sensors between conversions, minimizing the system?s power consumption. The AD7794/AD7795 can operate with either an internal clock or an external clock. The output data rate from each part can vary from 4.17 Hz to 470 Hz.Both parts operate with a power supply from 2.7 V to 5.25 V. The B-grade parts (AD7794 and AD7795) are specified for a temperature range of ?40?C to +105?C while the C-grade part (AD7794) is specified for a temperature range of ?40?C to +125?C. They consume a current of 400 ?A typical and are housed in a 24-lead TSSOP.Applications Temperature measurement Pressure measurement Weigh scales Strain gage transducers Gas analysis

BOARD EVALUATION

DC1751A-F: Demo Board for the LTM9006-14 14-Bit, 25Msps Low Power Octal ADCs.

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

Target Development Board for MSP430FR599x MCUs with 80-pins (microcontroller not included)

DC690A: Demo Board for the LT3420 Photoflash Capacitor Chargers with Automatic Refresh.

DC710A: Demo Board for the LTC5531 Precision 300MHz to 7GHz RF Detector with Shutdown and Offset Adjustment.

DC711A-A: Demo Board for the LT3468 Photoflash Capacitor Chargers in ThinSOT.

The LT5528 is a direct I/Q modulator designed for high performance wireless applications, including wireless infrastructure. It allows direct modulation of an RF signal using differential baseband I and Q signals. It supports PHS, GSM, EDGE, TD-SCDMA, CDMA, CDMA2000, W-CDMA and other systems. It may also be con? gured as an image reject up-converting mixer, by applying 90? phase-shifted signals to the I and Q inputs. The I/Q baseband inputs consist of voltage-to-current converters that in turn drive double-balanced mixers. The outputs of these mixers are summed and applied to an on-chip RF transformer, which converts the differential mixer signals to a 50? single-ended output. The four balanced I and Q baseband input ports are intended for DC coupling from a? source with a common-mode voltage level of about 0.5V. The LO path consists of an LO buffer with single-ended input, and precision quadrature generators that produce the LO drive for the mixers. The supply voltage range is 4.5V to 5.25V.Applications Infrastructure Tx for DCS, PCS and UMTS Bands Image Reject Up-Converters for PCS and UMTS Bands Low-Noise Variable Phase-Shifter for 1.5GHz to 2.4GHz Local Oscillator Signals

The LTC4063 is a standalone linear charger for single cell lithium-ion batteries with an adjustable low dropout linear regulator (LDO). The adjustable LDO regulates an output voltage between 1.2V to 4.2V at up to 100mA load current. When the input supply (wall adapter or USB supply) is removed, the LDO regulates the output voltage without interruption. The battery charger and LDO regulator can be enabled individually.No external sense resistor or external blocking diode is required for charging due to the internal MOSFET architecture. Internal thermal feedback regulates the charge current to maintain a constant die temperature during high power operation or high ambient temperature conditions. The float voltage is fixed at 4.2V and the charge current is programmed with an external resistor. Charge termination methods include minimum charge current or maximum time. With power applied, the LTC4063 can be put into shutdown mode to reduce the supply current to 35?A and the battery drain current to less than 2?A.Other features include smart recharge, undervoltage lockout, LDO current limiting and a charge status pin to indicate when the charge cycle has completed.Applications Handheld Computers Portable MP3 Players Digital Cameras