DC473A: Demo Board for the LTC1702A - Dual 550kHz Synchronous 2-Phase Switching Regulator Controller.

The LTC3246 is a switched capacitor buck-boost DC/DC converter with integrated watchdog timer. The device produces a regulated output (3.3V, 5V or adjustable) from a 2.7V to 38V input. Switched capacitor fractional conversion is used to maintain regulation over a wide range of input voltage. Internal circuitry automatically selects the conversion ratio to optimize efficiency as input voltage and load conditions vary. No inductors are required.The LTC3246?s reset time and watchdog timeout may be set without external components, or adjusted using external capacitors. A windowed watchdog function is used for high reliability applications. The reset input can be used for additional supply monitoring or be configured as a pushbutton reset.Low operating current (20?A without load, 1.5?A in shutdown) and low external parts count make the LTC3246 ideally suited for low power, space constrained automotive/ industrial applications. The device is short-circuit and overtemperature protected and is available in a thermally enhanced 16-pin MSOP package.Applications Automotive ECU/CAN Transceiver Supplies Industrial/Telecom Housekeeping Supplies Low Power 12V to 5V Conversion

Demonstration circuits 1053A-E through 1053A-H exercise the LTC3526L family of high efficiency synchronous boost converters, and are capable of operating with an input voltage range from 0.8V to 5.5V. The 2 × 2 mm DFN thermally enhanced package, high switching frequency (1MHz or 2MHz) and 550mA internal power switches provide a very tiny solution. The LTC3526L family also features output disconnect, and the input voltage can be greater or less than the output voltage. DC1053A-G features the LTC3526L-2 (Burst mode operation) and the DC1053A-H features the LTC3526LB-2 (Burst mode defeated). Both have a 2MHz switching frequency and use a 2.2µH inductor.

The AD9125 is a dual, 16-bit, high dynamic range TxDAC+? digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems

Demonstration circuit 2583 is an Ethernet Alliance™ certified IEEE 802.3bt compliant Power over Ethernet (PoE) powered device (PD). It features the LT4294 PD interface controller and the LT4321 PoE ideal diode bridge controller.

The HMC618ALP3E is a GaAs pHEMT MMIC Low Noise Amplifier that is ideal for Cellular/3G and LTE/WiMAX/4G basestation front-end receivers operating between 1.2 - 2.2 GHz. The amplifier has been optimized to provide 0.75 dB noise figure, 19 dB gain and +36 dBm output IP3 from a single supply of +5V. Input and output return losses are excellent and the LNA requires minimal external matching and bias decoupling components. The HMC618ALP3E shares the same package and pinout with the HMC617LP3E 0.55 - 1.2 GHz LNA. The HMC618ALP3E can be biased with +3V to +5V and features an externally adjustable supply current which allows the designer to tailor the linearity performance of the LNA for each application. The HMC618ALP3E offers improved noise figure versus the previously released HMC375LP3(E) and the HMC382LP3(E).Applications Cellular/3G and LTE/WiMAX/4G BTS & Infrastructure Repeaters and Femto Cells Public Safety Radio

RF Amplifier dig Variable-Gain

The ADG741 is a monolithic CMOS SPST switch. It is designed on an advanced submicron process that provides low power dissipation yet high switching speed, low on resistance, low leakage currents and -3 dB bandwidths of greater than 200 MHz can be achieved.The ADG741 can operate from a single 1.8 V to 5.5 V supply, making it ideal for use in battery-powered instruments and with Analog Devices' new generation of DACs and ADCs.APPLICATIONS Battery Powered Systems Communication Systems Sample Hold Systems Audio Signal Routing Video Switching Mechanical Reed Relay Replacement

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The LTC1068 product family consists of four monolithic clock-tunable filter building blocks. Each product contains four matched, low noise, high accuracy 2nd order switched-capacitor filter sections. An external clock tunes the center frequency of each 2nd order filter section. The LTC1068 products differ only in their clock-to-center frequency ratio. The clock-to-center frequency ratio is set to 200:1 (LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or 25:1 (LTC1068-25). External resistors can modify the clock-to-center frequency ratio. High performance, quad 2nd order, dual 4th order or 8th order filters can be designed with an LTC1068 family product. Designing filters with an LTC1068 product is fully supported by FilterCAD? filter design software for Windows. The LTC1068 products are available in a 28-pin SSOP surface mount package. A customized version of an LTC1068 family product can be obtained in a 16-lead SO package with internal thin-film resistors. Please contact LTC Marketing for details.Applications Lowpass or Highpass Filters: LTC1068-200, 0.5Hz to 25kHz; LTC1068, 1Hz to 50kHz; LTC1068-50, 2Hz to 50kHz; LTC1068-25, 4Hz to 200kHz Bandpass or Bandreject (Notch) Filters: LTC1068-200, 0.5Hz to 15kHz; LTC1068, 1Hz to 30kHz; LTC1068-50, 2Hz to 30kHz; LTC1068-25, 4Hz to 140kHz