The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The LTC1068 product family consists of four monolithic clock-tunable filter building blocks. Each product contains four matched, low noise, high accuracy 2nd order switched-capacitor filter sections. An external clock tunes the center frequency of each 2nd order filter section. The LTC1068 products differ only in their clock-to-center frequency ratio. The clock-to-center frequency ratio is set to 200:1 (LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or 25:1 (LTC1068-25). External resistors can modify the clock-to-center frequency ratio. High performance, quad 2nd order, dual 4th order or 8th order filters can be designed with an LTC1068 family product. Designing filters with an LTC1068 product is fully supported by FilterCAD? filter design software for Windows. The LTC1068 products are available in a 28-pin SSOP surface mount package. A customized version of an LTC1068 family product can be obtained in a 16-lead SO package with internal thin-film resistors. Please contact LTC Marketing for details.Applications Lowpass or Highpass Filters: LTC1068-200, 0.5Hz to 25kHz; LTC1068, 1Hz to 50kHz; LTC1068-50, 2Hz to 50kHz; LTC1068-25, 4Hz to 200kHz Bandpass or Bandreject (Notch) Filters: LTC1068-200, 0.5Hz to 15kHz; LTC1068, 1Hz to 30kHz; LTC1068-50, 2Hz to 30kHz; LTC1068-25, 4Hz to 140kHz

The HMC356LP3(E) is a high dynamic range GaAs PHEMT MMIC Low Noise Amplifier is ideal for GSM & CDMA cellular basestation and Mobile Radio front-end receivers operating between 350 and 550 MHz. This LNA has been optimized to provide 1 dB noise figure, 17 dB gain and +38 dBm output IP3 from a single supply of +5V @ 104 mA. Input and output return losses are 15 dB typical, with the LNA requiring only four external components to optimize the RF input match, RF ground and DC bias.Applications GSM 450 & GSM 480 CDMA 450 Private Land Mobile Radio

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The AD7124-8 is a low power, low noise, completely integratedanalog front end for high precision measurement applications.The device contains a low noise, 24-bit ?-? analog-to-digitalconverter (ADC), and can be configured to have 8 differentialinputs or 15 single-ended or pseudo differential inputs. The onchiplow gain stage ensures that signals of small amplitude canbe interfaced directly to the ADC.One of the major advantages of the AD7124-8 is that it gives theuser the flexibility to employ one of three integrated powermodes. The current consumption, range of output data rates,and rms noise can be tailored with the power mode selected.The device also offers a multitude of filter options, ensuring thatthe user has the highest degree of flexibility.The AD7124-8 can achieve simultaneous 50 Hz and 60 Hzrejection when operating at an output data rate of 25 SPS (singlecycle settling), with rejection in excess of 80 dB achieved at loweroutput data rates.The AD7124-8 establishes the highest degree of signal chainintegration. The device contains a precision, low noise, lowdrift internal band gap reference and accepts an externaldifferential reference, which can be internally buffered. Otherkey integrated features include programmable low drift excitationcurrent sources, burnout currents, and a bias voltage generator,which sets the common-mode voltage of a channel to AVDD/2.The low-side power switch enables the user to power downbridge sensors between conversions, ensuring the absoluteminimal power consumption of the system. The device alsoallows the user the option of operating with either an internalclock or an external clock.The integrated channel sequencer allows several channels to beenabled simultaneously, and the AD7124-8 sequentially convertson each enabled channel, simplifying communication with thedevice. As many as 16 channels can be enabled at any time, achannel being defined as an analog input or a diagnostic suchas a power supply check or a reference check. This uniquefeature allows diagnostics to be interleaved with conversions.The AD7124-8 also supports per channel configuration. Thedevice allows eight configurations or setups. Each configurationconsists of gain, filter type, output data rate, buffering, andreference source. The user can assign any of these setups on achannel by channel basis.The AD7124-8 also has extensive diagnostic functionalityintegrated as part of its comprehensive feature set. Thesediagnostics include a cyclic redundancy check (CRC), signalchain checks, and serial interface checks, which lead to a morerobust solution. These diagnostics reduce the need for externalcomponents to implement diagnostics, resulting in reducedboard space needs, reduced design cycle times, and cost savings.The failure modes effects and diagnostic analysis (FMEDA) of atypical application has shown a safe failure fraction (SFF) greaterthan 90% according to IEC 61508.The device operates with a single analog power supply from 2.7 Vto 3.6 V or a dual 1.8 V power supply. The digital supply has arange of 1.65 V to 3.6 V. It is specified for a temperature rangeof ?40?C to +125?C. The AD7124-8 is housed in a 32-leadLFCSP package.Note that, throughout this data sheet, multifunction pins, suchas DOUT/RDY, are referred to either by the entire pin name orby a single function of the pin, for example, RDY, when onlythat function is relevant.Applications Temperature measurement Pressure measurement Industrial process control Instrumentation Smart transmitters

Demonstration circuit 2672A-A is a complete non-isolated 48V input, dual-output, high efficiency, high density µModule regulator with 30V to 58V input range. Each output can supply 25A maximum load current. The demo board has a LTM4664 µModule regulator, which is a dual 25A or single 50A step-down regulator with digital power system management. Please see the LTM4664 datasheet for more detailed information. DC2672A-A powers up to default settings and produces power based on configuration resistors without the need for any serial bus communication. This allows easy evaluation of the DC/DC converter. To fully explore the extensive power system management features of the part, download the GUI software LTpowerPlay™ onto your PC and use ADI’s I2C/SMBus/PMBus dongle DC1613A to connect to the board. LTpowerPlay allows the user to reconfigure the part on the fly and store the configuration in EEPROM, view telemetry of voltage, current, temperature and fault status.

The LTC2631 is a family of 12-, 10-, and 8-bit voltage-output DACs with an integrated, high accuracy, low-drift reference in an 8-lead TSOT-23 package. It has a rail-to-rail output buffer that is guaranteed monotonic.The LTC2631-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2631-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. A 10ppm/?C reference output is available at the REF pin.Each DAC can also operate in External Reference mode, in which a voltage supplied to the REF pin sets the fullscale output.The LTC2631 DACs use a 2-wire, I2C-compatible serial interface. The LTC2631 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz).The LTC2631 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale after power-up.Applications Mobile Communications Process Control and Industrial Automation Automatic Test Equipment Portable Equipment Automotive Optical Networking

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+? family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/?C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 ? VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ?2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 ?A(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ?2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/?C typical temperature coefficient. 5 ppm/?C maximum temperature coefficient. Two Package Options. 2.00 mm ? 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

The ADCMP604 / ADCMP605?are very fast comparators fabricated on the Analog Devices, Inc. proprietary XFCB2 process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE ? 0.5 V to VCCI + 0.2 V, low noise, LVDS-compatible output drivers, and TTL/CMOS latch inputs with adjustable hysteresis and/or shut-down inputs.The devices offer 1.5 ns propagation delays with 1 ps rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps.A flexible power supply scheme allows the devices to operate with a single 2.5 V positive supply and a ?0.5 V to +2.7 V input signal range up to a 5.5 V positive supply with a ?0.5 V to +5.7 V input signal range. Split input/output supplies, with no sequencing restrictions on the ADCMP605, support a wide input signal range with greatly reduced power consumption.The LVDS-compatible output stage is designed to drive any standard LVDS input. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option.The ADCMP604 is available in a 6-lead SC70 package, and the ADCMP605 is available in a 12-lead LFCSP.APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)

The LTC2752 is a dual 16-bit multiplying serial-input, current-output digital-to-analog converter. It operates from a single 3V to 5V supply and is guaranteed monotonic over temperature. The LTC2752A provides full 16-bit performance (?1LSB INL and DNL, max) over temperature without any adjustments. This SoftSpan? DAC offers six output ranges (up to ?10V) that can be programmed through the 3-wire SPI serial interface, or pinstrapped for operation in a single range. Any on-chip register (including DAC output-range settings) can be read for verification in just one instruction cycle; and if you change register content, the altered register will be automatically read back during the next instruction cycle. Voltage-controlled offset and gain adjustments are also provided; and the power-on reset circuit and CLR pin both reset the DAC outputs to 0V regardless of output range.Applications High Resolution Offset and Gain Adjustment Process Control and Industrial Automation Automatic Test Equipment Data Acquisition Systems