The ADRF5549 is a dual-channel, integrated, RF front-end multichip module designed for time division duplexing (TDD) applications that operates from 1.8 GHz to 2.8 GHz. The ADRF5549 is configured in dual channels with a cascading, two-stage, low noise amplifier (LNA) and a high power, silicon single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.4 dB and a high gain of 35 dB with an output third-order intercept point (OIP3) of 32 dBm typical.In low gain mode, one stage of the two-stage LNA is in bypass mode providing 17 dB of gain at a lower current of 35 mA. In power-down mode, the LNAs are turned off, and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.6 dB and handles a long-term evolution (LTE) full lifetime average (9 dB peak to average ratio (PAR)) of 40 dBm and 43 dBm for a 9 dB PAR LTE single event (ApplicationsWireless InfrastructureTDD massive multiple input and multiple output (MIMO) and active antenna systemsTDD-based communication systems

The ADRF5740 is a silicon, 4-bit digital attenuator with 22 dB attenuation control range in 2 dB steps.The ADRF5740 operates from 10 MHz to 60 GHz with less than 3.3 dB of insertion loss and with ?(0.2 + 7.0% of attenuation state) of attenuation accuracy at 55 GHz. The ATTIN port of the ADRF5740 has an RF input power handling capability of 24 dBm average and 24 dBm peak for all states.The ADRF5740 requires a dual supply voltage of +3.3 V and ?3.3 V. The ADRF5740 features parallel mode control, and CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5740 RF ports are designed to match a characteristic impedance of 50 ?. The ADRF5740 comes in a 16-terminal, 2.5 mm ? 2.5 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF6821 is a highly integrated, dual radio frequency (RF) input, zero intermediate frequency (IF)/low IF RFIC receiverwith a quadrature demodulator, digital step attenuator (DSA),IF linear amplifiers, an integrated, fractional-N phase-locked loop (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication digital predistortion (DPD) systems.The high isolation 2:1 RF switch and on-chip wideband RFbalun enable the ADRF6821 to support two single-ended, 50 ? terminated RF inputs. A programmable attenuator ensures anoptimal differential RF input level to the high linearity demodulatorcore. The integrated attenuator offers an attenuation range of 15 dB with a step size of 1 dB. High linearity IF amplifiers follow the demodulator and provide an interface to the next componentin the chain, typically an analog-to-digital converter (ADC).The ADRF6821 offers two alternatives for generating thedifferential local oscillator (LO) input signal: internally viathe on-chip fractional-N synthesizer with low phase noiseVCOs or externally via a low phase noise LO signal. Theintegrated synthesizer enables continuous LO coverage from 450 MHz to 2800 MHz. The PLL reference input supports awide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).When selected, the output of the internal fractional-N synthesizeris applied to a divide by 2, quadrature phase splitter. From theexternal LO path, a 2? LO signal can be used with the divide by 2,quadrature phase splitter to generate the quadrature LO inputs to the mixers.The ADRF6821 is fabricated using an advanced silicon germanium(SiGe), bipolar complementary metal oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS compliant,8 mm ? 8 mm LFCSP package with an exposed pad. Performanceis specified over the ?40?C to +105?C case temperature range.Applications Cellular W-CDMA/GSM/LTE DPD receivers? Microwave, point to point radios

The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual channel transmitters, observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 2G, 3G and 4G macro-cell base stations, and active antenna, applications.The transmitters use an innovative direct conversion modulator that achieves multi-carrier macro-base-station quality performance and very low power. In 3G/4G mode, the maximum large-signal bandwidth is 200MHz. In MC-GSM mode, which has higher in-band SFDR, the maximum large-signal bandwidth is 75MHz.The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated. The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer is used to generate the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All VCO and loop filter components are integrated.The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode. The core of the ADRV9008-2 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The LTC2325-14 is a low noise, high speed quad 14-bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC2325-14 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2325-14 achieves ?1LSB INL typical, no missing codes at 14 bits and 81dB SNR.The LTC2325-14 has an onboard low drift (20ppm/?C max) 2.048V or 4.096V temperature-compensated reference. The LTC2325-14 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 5Msps per channel throughput with one cycle latency makes the LTC2325-14 ideally suited for a wide variety of high speed applications. The LTC2325-14 dissipates only 45mW per channel and offers nap and sleep modes to reduce the power consumption to 26?W for further power savings during inactive periods.Applications High Speed Data Acquisition Systems Communications Optical Networking Multiphase Motor Control

The LTC2320-12 is a low noise, high speed octal 12?bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC2320?12 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2320-12 achieves ?0.25LSB INL typical, no missing codes at 12 bits and 77dB SNR.The LTC2320-12 has an onboard low drift (20ppm/?C max) 2.048V or 4.096V temperature-compensated reference. The LTC2320-12 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 1.5Msps per channel throughput with no latency makes the LTC2320-12 ideally suited for a wide variety of high speed applications. The LTC2320-12 dissipates only 20mW per channel and offers nap and sleep modes to reduce the power consumption to 26?W for further power savings during inactive periods.Applications High Speed Data Acquisition Systems Communications Remote Data Acquisition Imaging Optical Networking Automotive Multiphase Motor Control

The LTC6373 is a precision instrumentation amplifier with fully differential outputs which includes a closely matched internal resistor network to achieve excellentCMRR, offset voltage, gain error, gain drift, and gain nonlinearity. The user can easily program the gain to one of seven available settings through a 3-bit parallel interface(A2 to A0). The 8th state puts the part in shutdown which reduces the current consumption to 220?A. Unlike a conventional voltage feedback amplifier, the LTC6373maintains nearly the same bandwidth across all its gain settings.The LTC6373 features fully differential outputs to drive high performance, differential-input ADCs. The output common mode voltage is independently adjustable viathe VOCM pin. The combination of high impedance inputs, DC precision, low noise, low distortion, and high-speed differential ADC drive makes the LTC6373 an ideal candidate for optimizing data acquisition systems.The LTC6373 is available in a 12-lead 4mm ? 4mm DFN (LFCSP) package and is fully specified over the ?40?C to 125?C temperature range.Applications Data Acquisition Systems Biomedical Instrumentation Test and Measurement Equipment Differential ADC Drivers Single-Ended-to-Differential Conversion Multiplexed Applications

The LT8650S is a dual step-down regulator that delivers up to 4A of continuous current from both channels and supports loads up to 6A from each channel. The LT8650S features the second generation Silent Switcher architecture to minimize EMI emissions while delivering high efficiency at high switching frequencies. This includes integration of bypass capacitors to optimize high frequency current loops and make it easy to achieve advertised EMI performance by eliminating layout sensitivity.The fast, clean, low-overshoot switching edges enable high efficiency operation even at high switching frequencies, leading to a small overall solution size. Peak current mode control with a 40ns minimum on-time allows high step down ratios at high switching frequencies.Burst Mode operation features a 6.2?A quiescent current resulting in high efficiency at low output currents, forced continuous mode allows fixed switching frequency operation over the entire output load range, and spread spectrum operation can further reduce EMI emissions. External VC pins allow optimal loop compensation for fast transient response. The VC pins can also be used for current sharing and the CLKOUT pin enables synchronizing two LT8650S chips to generate a 4-phase, 16A supply.APPLICATIONS General Purpose Step-Down Automotive and Industrial Supplies

The LTC2335-18 is an 18-bit, low noise 8-channel multiplexed successive approximation register (SAR) ADC with differential, wide common mode range inputs. Operating from a 5V low voltage supply, flexible high voltage supplies, and using the internal reference and buffer, this SoftSpan? ADC can be configured on a conversion-by-conversion basis to accept ?10.24V, 0V to 10.24V, ?5.12V, or 0V to 5.12V signals on any channel. Alternately, the ADC may be programmed to cycle through a sequence of channels and ranges without further user intervention.The wide input common mode range and 118dB CMRR of the LTC2335-18 analog inputs allow the ADC to directly digitize a variety of signals, simplifying signal chain design. This input signal flexibility, combined with ?3LSB INL, no missing codes at 18 bits, and 96.7dB SNR, makes the LTC2335-18 an ideal choice for many high voltage applications requiring wide dynamic range.The LTC2335-18 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces.Applications Programmable Logic Controllers Industrial Process Control Power Line Monitoring Test and Measurement