The ADMV1017 is a silicon germanium (SiGe), microwave, upconverter and downconverter optimized for 5G radio designs operating in the 24 GHz to 29.5 GHz frequency range.The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from differential baseband I/Q input signals, as well as single-sideband (SSB) upconversion from complex intermediate frequency (IF) inputs. Alternatively, the differential baseband I/Q input path can be disabled and a modulated, single-ended, complex IF signals from 3 GHz to 10.5 GHz can be fed to the IF path. These signals can then be upconverted to 24 GHz to 29.5 GHz while rejecting the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) provides adjustment of the quadrature phase to allow optimum sideband rejection. In addition, the SPI interface allows powering down the output envelope detector to reduce power consumption when carrier feed through optimization is not necessary.The downconverter offers two modes of frequency translation. The device is capable of direct quadrature demodulation to differential baseband I/Q output signals, as well as image rejection downconversion to a single-ended complex IF output carrier frequency. The differential baseband outputs can be dc-coupled. More typically, however, the I/Q outputs are ac-coupled with a sufficiently low high-pass corner frequency to ensure adequate demodulation accuracy. The I/Q baseband output common-mode voltage is programmable between 0.75 V and 2.15 V. The SPI interface provides fine adjustment of the quadrature phase to optimize I/Q demodulation performance. Alternatively, the baseband I/Q outputs can be disabled, and the I/Q signals can be passed through an on-chip, active balun to provide two, single-ended, complex IF outputs between 3 GHz and 10.5 GHz. When the device is used as an image rejecting down-converter, the unwanted image term is typically rejected to better than 25 dBc below the desired sideband. The ADMV1017 offers a square law power detector to allow monitoring of the power levels at the mixer inputs. The detector output provides closed-loop control of the RF digital step attenuator via an external automatic gain control (AGC) loop.The ADMV1017 upconverter and downconverter is housed in a compact, thermally enhanced, 9 mm ? 8 mm, land grid array (LGA) package. The ADMV1017 operates over the ?40?C to +95?C case temperature range. Throughout the figures in the data sheet, Rx means receiver and Tx means transmitter.APPLICATIONS5G applicationsPoint to point microwave radiosRadar and electronic warfare systemsInstrumentation and automatic test equipment (ATE)

The ADMV4530 is a highly integrated upconverter with an in-phase/quadrature (I/Q) mixer that is ideally suited for next generation Ka band satellite communications.An integrated low phase noise, fractional-N phase-locked loop (PLL) with a voltage controlled oscillator (VCO) and internal 2? multiplier generate the necessary on-chip local oscillator (LO) signal for the I/Q mixer, eliminating the need for external frequency synthesis. The VCO uses an internal autocalibration routine that allows the PLL to select the necessary settings and locks in approximately 100 ?s.The single-ended reference input to the PLL operates up to 500 MHz and features internal reference dividers and a multiplier for added flexibility. Additionally, the phase frequency detector (PFD) comparison frequency can be up to 250 MHz for integer mode and 160 MHz for fraction-N mode.The upconverter consists of an I/Q mixer that can operate in either I/Q mode with 500 MHz of bandwidth or in IF mode up to 3 GHz of bandwidth, which allows various radio architectures and backward compatibility with legacy systems.Immediately following the I/Q mixer are stages of gain and variable attenuation. The configuration can achieve a minimum 1 dB compression point (P1dB) compression point of 19 dBm, eliminating the need for external stages of gain.A programmable 4-wire serial port interface (SPI) allows adjustment of the quadrature phase for optimum sideband suppression. In addition, the SPI allows nulling of LO feedthrough in IF mode. In I/Q mode, the LO feedthrough can be nulled by applying external dc offset to the differential baseband I/Q inputs.An IF automatic gain control (AGC) adjusts the IF variable gain amplifier (VGA) to compensate for input power variations. During normal operation, this AGC feature can be enabled or disabled via the SPI. When disabled during normal operation, the AGC feature only works on a test tone during power-down mode to track temperature variations.The ADMV4530 upconverter comes in a RoHs compliant, 6 mm ? 6 mm, 40-terminal land grid array (LGA) package. The ADMV4530 operates over the ?40?C to +85?C case temperature range.Applications Satellite communication Point to point microwave communication

ADI 47.2 GHz to 48.2 GHz TX/RX Dual Polarization Beamformer

The ADMV4821 is a silicon germanium (SiGe), 24 GHz millimeterwave (mmW) to 29.5 GHz mmW 5G beamformer. The RF IC is highly integrated and contains 16 independent channels with both transmit and receive functionality. The ADMV4821 supports eight horizontal and eight vertical polarized antennas via the independent RFV and RFH inputs/outputs common pins.In transmit mode, both the RFV and RFH input signals are split via two independent 1:8 power splitters and pass through the eight, independent, corresponding transmit channels. In this mode, each channel includes a vector modulator (VM) to control the phase and two digital variable gain amplifiers (DVGAs) to control the amplitude.In receive mode, input signals pass through two sets of eight receive channels (either vertical or horizontal) and are combined via one independent 8:1 combiner connected to the RFV pin and one independent 8:1 combiner connected to the RFH pin. In this mode, each channel includes a VM to control the phase and a DVGA to control the amplitude.The VM provides a full 360? phase adjustment range in either transmit or receive mode. The VM provides six bits of resolution for 5.625? phase steps.In transmit mode, the total DVGA dynamic range adjustment range is 32.4 dB. The DVGAs provide five bits or six bits of resolution, resulting in 1.0 dB or 0.5 dB amplitude steps, respectively.In receive mode, the DVGA allows for 17.1 dB of dynamic range adjustment. The DVGA also provides six bits of resolution, resulting in 0.5 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range.The transmitter channels contain individual power detectors to detect and calibrate the gain for each channel as well as the channel to channel gain mismatch. Directly connect the ADMV4821 RF ports to a patch antenna to create a dual polarization mmW 5G subarray.Users can program the ADMV4821 by using a 3-wire or 4-wire serial port interface (SPI). The integrated on-chip low dropout (LDO) regulator generates the 1.8 V supply for the SPI circuitry to reduce the number of supply domains required. There are various SPI modes to enable fast startup and control during normal operation.Users can either set the amplitude and phase for each channel individually or program multiple channels simultaneously by using the on-chip memory for beamforming. The on-chip memory can store up to 256 beam positions, which can be allocated for either transmitter or receiver mode in any combination. In addition, four address pins allow SPI control of up to 16 devices on the same serial lines. Dedicated horizontal and vertical polarization load pins also synchronize all devices in the same array. There is a horizontal and vertical polarization transmit and receive mode control pins (TRXV and TRXH) for fast switching between transmit and receive mode.The ADMV4821 comes in a compact, thermally enhanced 10 mm ? 10 mm, RoHs compliant land grid array (LGA) package. The ADMV4821 operates over the ?40?C to +95?C case temperature range. This LGA package allows users to heat-sink the ADMV4821 from the top side of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).Throughout the figures in the data sheet, Tx means transmit (or transmitter) and Rx means receive (or receiver).APPLICATIONS5G applicationsBroadband communicationTest and measurementAerospace and defense

The ADN4600 is an asynchronous, nonblocking crosspoint switch with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 4.25 Gbps.The receive inputs provide programmable equalization with nine settings to compensate for up to 30 in. of FR4 and programmable pre-emphasis with seven settings to compensate for up to 30 in. of FR4 at 4.25 Gbps.The ADN4600 nonblocking switch core implements an 8 ? 8 crossbar and supports independent channel switching through the I2C control interface. Every channel implements an asynchronous path supporting NRZ data rates from dc to 4.25 Gbps. Each channel is fully independent of other channels. The ADN4600 has low latency and very low channel-to-channel skew.The main application for the ADN4600 is to support switching on the backplane, line card, or cable interface sides of serial links.The ADN4600 is packaged in a 9 mm ? 9 mm, 64-lead LFCSP package and operates from ?40?C to +85?C.APPLICATIONS 1?, 2?, 4? FibreChannel XAUI Gigabit Ethernet over backplane 10GBase-CX4 InfiniBand? 50 ? cables

ADS122C04 evaluation module

Power Management IC Development Tools

Data Conversion IC Development Tools 2.2GSPS Interleaved ADC Eval Mod

Power Management IC Development Tools

Data Conversion IC Development Tools 2.2GSPS Interleaved ADC Eval Mod