Demonstration circuit 2350B features the LTC6813-1, 18-channel battery-stack monitor. Multiple boards can be linked through a 2-wire isolated serial interface (isoSPI™) to monitor a long series of cells in a stack. The DC2350B demo board also features reversible isoSPI enabling a redundant communication path. The PCB, components, and DuraClik connectors are optimized for low EMI susceptibility and emissions. The DC2350B can communicate to a PC by connecting a DC2792B dual master isoSPI together with DC2026C Linduino® One. The DC2026 must be loaded with the appropriate program (called a sketch) to control the battery-stack monitor IC and receive data through a USB serial port. The DC2026 provides a standard SPI interface which can be translated to isoSPI and then connected to a DC2350B isoSPI port (J4 or J5 connector). The DC2792B companion board provides two SPI-isoSPI channels for reversible operation.

The LTC2873 is a robust pin-configurable multiprotocol transceiver that supports RS232, RS485, and RS422 protocols while operating on a single 3V to 5.5V supply. The LTC2873 can be configured as a half-duplex RS485 transceiver or as an RS232 transceiver using the same two bus pins.A pin-controlled integrated termination resistor allows for easy interface reconfiguration, eliminating external resistors and control relays. Loopback mode steers the driver inputs to the receiver outputs for diagnostic self-test. The RS485 receiver supports up to 256 nodes per bus, and features full failsafe operation for floating, shorted or terminated inputs.An integrated DC/DC boost converter uses a tiny 2mm ? 1.6mm inductor and one capacitor, eliminating the need for multiple supplies when driving RS232 levels.Applications Software Selectable RS232/RS485/RS422 Interface Industrial Sensors and Actuators Alarm Systems Traffic Control and Monitoring Highway Signs and Jumbo Displays

Demonstration circuit 2365A highlights the LTC2358 family of buffered input ADCs. The LTC2358/LTC2357/LTC2353/LTC2333 are low noise, high speed, 16-/18- bit successive approximation register (SAR) ADCs with integrated front end buffers. These ADCs accept a wide common mode range. Pico-amp inputs and high CMRR enable these ADCs to connect directly to a wide range of sensors without compromising measurement accuracy. The following text refers to the LTC2358-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. The LTC2358-18 has a flexible SoftSpan™ interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. An internal 2.048V reference and 2X buffer simplify basic operation while an external reference can be used to increase the input range and the SNR of the ADC.

Demonstration circuit 2365A highlights the LTC2358 family of buffered input ADCs. The LTC2358/LTC2357/LTC2353/LTC2333 are low noise, high speed, 16-/18-bit successive approximation register (SAR) ADCs with integrated front end buffers. These ADCs accept a wide common mode range. Pico-amp inputs and high CMRR enable these ADCs to connect directly to a wide range of sensors without compromising measurement accuracy. The demo manual refers to the LTC2358-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. The LTC2358-18 has a flexible SoftSpan™ interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. An internal 2.048V reference and 2X buffer simplify basic operation while an external reference can be used to increase the input range and the SNR of the ADC.

Demonstration circuit 2365A highlights the LTC2358 family of buffered input ADCs. The LTC2358/LTC2357/LTC2353/LTC2333 are low noise, high speed, 16-/18- bit successive approximation register (SAR) ADCs with integrated front end buffers. These ADCs accept a wide common mode range. Pico-amp inputs and high CMRR enable these ADCs to connect directly to a wide range of sensors without compromising measurement accuracy. The following text refers to the LTC2358-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. The LTC2358-18 has a flexible SoftSpan™ interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. An internal 2.048V reference and 2X buffer simplify basic operation while an external reference can be used to increase the input range and the SNR of the ADC.

The LTM4632 is an ultrathin triple output step-down ?Module? (power module) regulator to provide complete power solution for DDR-QDR4 SRAM. Operating from a 3.6V to 15V input voltage, the LTM4632 supports two ?3A output rails, both sink and source capable, for VDDQ and VTT, plus a 10mA low noise reference VTTR output. Both VTT and VTTR track and are equal to VDDQ/2. Housed in a 6.25mm ? 6.25mm ? 1.82mm LGA and 6.25mm ? 6.25mm ? 2.42mm BGA packages, the LTM4632 includes the switching controller, power FETs, inductors and support components. Alternatively, the power module can also be configured as a two phase single ?6A output VTT. Only a few ceramic input and output capacitors are needed to complete the design.The LTM4632 supports selectable Burst Mode operation (CH1 only) and output voltage tracking for supply rail sequencing. Its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability.Fault protection features include overvoltage input, overcurrent and overtemperature protection.The LTM4632 is RoHS compliant with Pb-free finish.Applications DDR Memory Power Supply General Purpose Point of Load Conversion Telecom, Networking and Industrial Equipment

DC236C-C: Demo Board for the LTC1628 High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator.

The ADF4153A is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. A sigma-delta (?-?) based fractional interpolator allows programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture isspecifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes theADF4196 suitable for pulse Doppler radar applications.The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (?-?) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Pulsed Doppler radar Instrumentation and test equipment Beam-forming/phased array systems

The ADF4355 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers permits operation from 54 MHz to 6800 MHz.The ADF4355 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate radio frequency (RF) output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4355 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4355 also contains hardware and software power-down modes.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation