The ADF4360-8 is an integrated integer-N synthesizer and voltagecontrolled oscillator (VCO). The ADF4360-8 center frequencyis set by external inductors. This allows a frequencyrange of between 65 MHz to 400 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.?

The ADF4371 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave voltage controlled oscillator (VCO) design allows frequencies from 62.5 MHz to 32 GHz to be generated.The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. To suppress the unwanted products of frequency multiplication, a harmonic filter exists between the multipliers and the output stages of RF16x and RF32x.Control of all on-chip registers is through a 3-wire interface. The ADF4371 operates with analog and digital power suppliesranging from 3.15 V to 3.45 V, and 5 V for the VCO power supply. The ADF4371 also contains hardware and software power-down modes. APPLICATIONS Wireless infrastructure (multicarrier global system for mobile communication (MC-GSM), 5 G) Test equipment and instrumentation Clock generation Aerospace and defense

The ADF5610 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference source. The wideband microwave voltage controlled oscillator (VCO) design permits frequency operation from 7300 MHz to 14600 MHz at a single radio frequency (RF) output. A series of frequency dividers with a differential frequency output allows operation from 57 MHz to 14600 MHz. Analog and digital power supplies for the PLL circuitry range from 3.1 V to 3.5 V, and the VCO supplies are between 4.75 V and 5.25 V. The charge pump supply voltage can be extended up to 3.6 V for improved frequency band overlap and extended upper frequency range.The ADF5610 has an integrated VCO with a fundamental frequency of 3650 MHz to 7300 MHz. These frequencies are internally doubled and routed to the RFOUT pin. An additional differential output allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to generate RF output frequencies as low as 57 MHz. A simple 3?wire serial port interface (SPI) provides control of all on-chip registers. To conserve power, this divider block can be disabled when not needed through the SPI interface. Likewise, the output power for both the single-ended output and the differential output are programmable via the VCO register settings. The ADF5610 also contains various power-down modes for the VCO circuitry and PLL circuitry.The integrated phase detector (PD) and delta-sigma (?-?) modulator, capable of operating at up to 100 MHz, permit wide loop bandwidths and fast frequency tuning with a typical spurious level of ?100 dBc.With phase noise levels from ?115 dBc/Hz at 7.3 GHz to ?109 dBc/Hz at 14.6 GHz, the ADF5610 is equipped to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. The low phase noise floor eliminates any contribution to modulator and mixer noise floor in transmitter applications.The ADF5610 is a PLL with integrated VCO. The device features an innovative programmable performance technology that enables the ADF5610 to tailor current consumption and corresponding noise performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved phase noise performance.Additional features of the ADF5610 include approximately 3 dBof RFOUT gain control in 1.5 dB steps and 5 dB of control onthe differential port in approximately 2.5 dB steps. Finally, the ?-?modulator with exact frequency mode enables users to generateoutput frequencies with 0 Hz frequency error.APPLICATIONSMilitary and defenseTest equipmentClock generationWireless infrastructureSatellite and very small aperture terminal (VSAT)Microwave radio

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of ?20 dBm to +13 dBm and ?20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM??Cortex?-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the?IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm ? 6 mm, 40-lead LFCSP and a 7 mm ? 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is ?40?C to +85?C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_CON is a programmable value that configures the internal LDO voltage that provides bias for the PA. For additional information on these bit settings, see the ADF7030-1 Software Reference Manual, which is the detailed programming guide for the device.Applications IEEE 802.15.4g (MR-FSK PHY)? Wireless M-Bus (EN 13757-4) Smart metering Security and building automation? Active tag asset tracking Industrial control Wireless sensor networks (WSNs)

The ADuCRF101 is a fully integrated, data acquisition solution that is designed for low power, wireless applications. It features a 12-bit analog-to-digital converter (ADC), a low power ARM Cortex?-M3 processor, a 862 MHz to 928 MHz and 431 MHz to 464 MHz RF transceiver, and Flash?/EE memory. The ADuCRF101 is packaged in a 9 mm ? 9 mm LFCSP.The data acquisition section consists of a 12-bit SAR ADC. The six inputs can be configured in single-ended or differential mode. When configured in single-ended mode, they can be used for ratiometric measurements on sensors that are powered, when required, from the internal low dropout regulator (LDO). An internal battery monitor channel and an on-chip temperature sensor are also available.This wireless data acquisition system is designed to operate in battery-powered applications where low power is critical. The device can be configured in normal operating mode or different low power modes under direct program control. In flexi mode, any peripheral can wake up the device and operate it. In hibernate mode, the internal wake-up timer remains active. In shutdown mode, only an external interrupt can wake up the device.The ADuCRF101 integrates a low power ARM Cortex-M3 processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS peak performance. The ARM Cortex-M3 processor also has a flexible 14-channel direct memory access (DMA) controller that supports communication peripherals, serial peripheral interface (SPI), UART, and I2C. Also provided on chip are 128 kB of nonvolatile Flash/EE memory and 16 kB of SRAM.A 16 MHz on-chip oscillator generates the system clock. This clock can be internally divided for the processor to operate at a lower frequency, thus saving power. A low power, internal 32 kHz oscillator is available and can be used to clock the four timers, as follows: two general-purpose timers, a wake-up timer, and a system watchdog timer.A range of communication peripherals can be configured, as required, in a specific application. These peripherals include UART, I2C, SPI, GPIO ports, PWM, and RF transceivers.The RF transceiver communicates in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands using multiple configurations.On-chip factory firmware supports in-circuit serial download via the UART, and nonintrusive emulation and program download are also supported via the serial wire interface. These features are incorporated into a low cost development system supporting this precision analog microcontroller family.The ADuCRF101 operates from 2.2 V to 3.6 V and is specified over an industrial temperature range of ?40?C to +85?C. It is available in a 64-lead LFCSP packageApplications Battery powered wireless sensor Medical telemetry systems Industrial and home automation Asset tracking Security systems (access systems) Health and fitness applications??

The ADuM7703 is a high performance, second-order, ?-? analog-to-digital converter (ADC) with an integrated low dropout (LDO) regulator that converts an analog input signal into a high speed, single-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler? technology. The device operates from a 4.5 V to 20 V power supply range (VDD1) and accepts a pseudo differential input signal of ?250 mV (?320 mV full-scale). The pseudo differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required.The analog input is continuously sampled by a high performance analog modulator and converted to a ones density digital output stream with a data rate of up to 21 MHz. The original information can be reconstructed with an appropriate sinc3 digital filter to achieve an 86 dB signal-to-noise ratio (SNR) at 78.1 kSPS with a 256 decimation rate and a 20 MHz master clock. The serial input and output operates from a 5 V or a 3.3 V supply (VDD2).The serial interface is digitally isolated. High speed complementary metal-oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, results in the on-chip isolation providing outstanding performance characteristics, superior to alternatives such as optocoupler devices. The ADuM7703 device is available in a 16-lead, wide-body SOIC with an operating temperature range of ?40?C to +125?C and an 8-lead, wide-body SOIC with an operating temperature range of ?40?C to +105?C.Applications Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Analog-to-digital and optoisolator replacement

Together with an external loop filter and a voltage controlled crystal oscillator (VCXO), the HMC1031 forms a complete clock generator solution targeted at low frequency jitter attenuation and reference clock generation applications.The HMC1031 features a low power integer N divider, support-ing divide ratios of 1, 5, and 10, which is controlled via external hardware pins and requires no serial port.The integrated phase detector and charge pump are capable of operating at up to 140 MHz, and a maximum VCXO input of 500 MHz ensures frequency compliance with a wide variety of system clocks and VCXOs.Additional features include an integrated lock detect indicator available on a dedicated hardware pin, and a built in power-down mode.The HMC1031 is housed in an 8-lead MSOP package.APPLICATIONS Low jitter clock generation Low bandwidth (BW) jitter attenuation Low frequency phase-locked loops PLL Frequency translation Oven controlled crystal oscillator (OCXO) frequency multiplier Phase lock clean high frequency references to 10 MHz equipment

The HMC1060LP3E is a BiCMOS ultra low noise quad-output linear voltage regulator targeted at high performance applications requiring superb power supply isolation.Maximum 500 mA of current, distributed between four independent outputs, enable the HMC1060LP3E to supply all of the power needs of Hittite's Wideband PLL with Integrated VCO products, such as the HMC830LP6GE.Although targeted at Hittite's Wideband PLLs with Integrated VCO products, the HMC1060LP3E makes an excellent general purpose regulator that supports adjustable output voltages ranging anywhere from 1.8V to 5.2V.An Integrated PTAT (Proportional To Absolute Temperature) feature enabled via an external pin, allows the HMC1060LP3E to scale the supply voltage with temperature in order to maximize phase noise and output power performance of Hittite's Wideband with Integrated VCO products, as well as other devices powered by the HMC1060LP3E.Integrated thermal protection disables the outputs of the HMC1060LP3E at extreme temperatures, until the device cools down, making the HMC1060LP3E a robust device capable of dealing with temporary and unforeseen scenarios including momentary short circuits and extreme temperatures.External Enable input provides a convenient way to power on or off all of the devices supplied by the HMC1060LP3E.The HMC1060LP3E is housed in a 3 ? 3 mm QFN SMT package.APPLICATIONS Ultra Low Noise Frequency Generation?(PLLs, VCOs, PLLs?with Integrated VCOs) RF & Mixed-Signal Supply

The HMC1061LC5 is a silicon germanium (SiGe), monolithic, fully differential, dual rank, track-and-hold amplifier that provides unprecedented bandwidth and dynamic range performance to wideband sampled signal systems. The track-and-hold amplifier offers precision signal sampling over an 18 GHz bandwidth, with 9-bit to 10-bit linearity from dc to beyond 5 GHz input frequency, 1.45 mV noise, and <70 fs random aperture jitter.The HMC1061LC5 can be clocked to 4 GSPS with minimal dynamic range loss. The track-and-hold amplifier can be used to expand the bandwidth and/or high frequency linearity of high speed analog to digital conversion and signal acquisition systems. Wideband data acquisition systems with multi GHz required bandwidth for a variety of applications, such as software defined radio, radar systems, electronic warfare (EW), electronic intelligence (ELINT), and automated test equipment (ATE).Applications RF ATE applications Digital sampling oscilloscopes RF demodulation systems Digital receiver systems High speed peak detectors Software defined radio Radar, electronic counter measures (ECM), and electronic intelligence systems High speed digital-to-analog converter (DAC) deglitching

The HMC1065LP4E is a compact GaAs MMIC Image Reject Low Noise Converter in a leadless RoHS compliant SMT package. This device provides a small signal conversion gain of 13 dB with 17 dBc of image rejection, and -2 dBm Input IP3. The HMC1065LP4E utilizes an RF LNA followed by an I/Q mixer which is driven by an active X2 multiplier. IF1 and IF2 mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of the unwanted sideband. The HMC1065LP4E is a much smaller alternative to hybrid style image reject downconverter assemblies and it eliminates the need for wire bonding by allowing the use of surface mount manufacturing techniques.APPLICATIONS Point-to-Point & Point-to-Multi-Point Radio Satellite Communications Sensors