The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The AD9154 is a quad, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.4 GSPS, permitting multicarrier generation up to the Nyquist frequency in baseband mode. The AD9154 includes features optimized for direct conversion transmit applications including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are?optimized to interface seamlessly with the ADRF6720-27 radio?frequency quadrature modulator (AQM) from Analog Devices,?Inc. In mix mode, the AD9154 DAC can reconstruct carriers in the second and third Nyquist Zones. A serial port interface (SPI)?provides the programming/readback of internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9154 is available in two different?88-lead LFCSP packages.PRODUCT HIGHLIGHTS? Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization. Small package size with a 12 mm ? 12 mm footprint.APPLICATIONS Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radio Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.

The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).The AD9172 is available in a 144-ball BGA_ED package.PRODUCT HIGHLIGHTS Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.APPLICATIONS Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE) Radars and jammers

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The ADP170 /?ADP171?/?ADP172 are low voltage input, low quiescentcurrent, low-dropout (LDO) linear regulators that operate from1.6 V to 3.6 V and provide up to 300 mA of output current. Thelow 55 mV dropout voltage at 300 mA load improves efficiencyand allows operation over a wide input voltage range. The low23 ?A of quiescent current at no load makes theADP170 / ADP171 / ADP172 ideal for battery-operated portableequipment.The ADP170 is capable of 31 fixed-output voltage options, ranging from 0.8 V to 3.0 V. ADP171 is an adjustableversion, which allows output voltages that range from 0.8 V to3.0 V via an external divider. The ADP170 / ADP171 areoptimized for stable operation with small 1 ?F ceramic outputcapacitors. Ideal for powering digital processors, the ADP170 / ADP171 exhibit good transient performance andoccupy minimal board space. Compared with commodity typesof LDOs, the ADP170 / ADP171 provide 20 dB to 40 dB betterpower supply rejection ratio (PSRR) at 100 kHz, making theADP170 / ADP171 an ideal power source for analog-to-digitalconverter (ADC) mixed-signal processor systems and allowinguse of smaller size bypass capacitors. In addition, low outputnoise performance without the need for an additional bypasscapacitor further reduces printed circuit board (PCB)component count.Short-circuit protection and thermal overload protectioncircuits prevent damage in adverse conditions. TheADP170 / ADP171 are available in tiny 5-lead TSOT for thesmallest footprint solution to meet a variety of portable powerapplications.APPLICATIONS Mobile phones Digital camera and audio devices Portable and battery-powered equipment DSP/FPGA/microprocessor supplies Post dc-dc regulation

The ADP1712?/ ADP1713 / ADP1714, available in a tiny, 5-lead TSOT package, are low dropout linear regulators that operate from 2.5 V to 5.5 V and provide up to 300 mA of output current. The low 170 mV dropout voltage at a 300 mA load improves efficiency and allows operation over a wide input voltage range. Using a novel scaling architecture, ground current is a very low 75 ?A when driving a 100 ?A load, making the ADP1712 / ADP1713 / ADP1714 ideal for battery-operated portable equipment.The ADP1712 / ADP1713 / ADP1714 are available in 16 fixed output voltage options. The ADP1712 is also available in an adjustable version, which allows output voltages that range from 0.8 V to 5 V via an external divider. The ADP1712 fixed version allows an external capacitor to be connected to program the soft-start time. The ADP1713 allows a reference bypass capacitor to be connected, which reduces output voltage noise and improves power supply rejection. The ADP1714 includes a tracking feature, which allows the output to follow an external voltage rail or reference.The ADP1712 / ADP1713 / ADP1714 are optimized for stable operation with small 2.2 ?F ceramic output capacitors, allowing good transient performance while occupying minimal board space. An enable pin controls the output voltage on all devices, and an undervoltage lockout circuit disables the regulator if IN drops below a minimum threshold. The parts also have short circuit protection and thermal overload protection, which prevent damage to the devices in adverse conditions.APPLICATIONS Mobile phones Digital camera and audio devices Portable and battery-powered equipment Post dc-dc regulation

The ADP1715 / ADP1716?are low dropout, CMOS linear regulators that operate from 2.5 V to 5.5 V and provide up to 500 mA of output current. Using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient response with just a small 2.2 ?F ceramic output capacitor.Three versions of this part are available, one with fixed output voltage options and variable soft start (ADP1715), one with adjustable output voltage and fixed soft start (ADP1715 Adjustable), and one with voltage tracking in fixed output voltage options (ADP1716). The fixed output voltage options are internally set to one of sixteen values between 0.75 V and 3.3 V; the adjustable output voltage can be set to any value between 0.8 V and 5.0 V by an external voltage divider connected from OUT to ADJ. The variable soft start uses an external capacitor at SS to control the output voltage ramp. Tracking limits the output voltage to the at-or-below voltage at the TRK pin.The ADP1715 / ADP1716 are available in 8-lead thermally enhanced MSOP packages, making them not only a very compact solution but also providing excellent thermal performance for applications requiring up to 500 mA of output current in a small, low profile footprint.APPLICATIONS Notebook computers Memory components Telecommunications equipment Network Equipment DSP/FPGA/?P supplies Instrumentation equipment/data acquisition systems

The ADP1754 /?ADP1755?are CMOS, low dropout linear regulators that operate from 1.6 V to 3.6 V and provide up to 1.2A of output current. These Low Vin?/ Vout LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5V down to 1.8V I/O rails, and powering core voltages down to 0.75V. Using an advanced proprietary architecture, they provide high power supply rejection, low noise, and achieve excellent line and load transient response with a small 4.7 ?F ceramic output capacitor.The ADP1754 is available in 7 fixed output voltage options. The ADP1755 is available in an adjustable version, which allows output voltages that range from 0.75 V to 3.0 V via an external divider. The ADP1754 / ADP1755 allows an external soft start capacitor to be connected to program the start-up. A power good output allows power system monitors to digitally check the health of the output power rail voltage.The ADP1754 / ADP1755 are available in a 16-lead, 4 mm ? 4 mm LFCSP, making them not only very compact solutions, but also providing excellent thermal performance for applications requiring up to 1.2A of output current in a small, low profile footprint.APPLICATIONS Server computers Memory components Telecommunications equipment Network equipment DSP/FPGA/microprocessor supplies Instrumentation equipment/data acquisition systems