The HMC802ALP3E is a broadband bidirectional 1-bitGaAs IC digital attenuator in a low cost leadless sur-face mount package. This single positive control linedigital attenuator utilizes off chip AC ground capac-itors for near DC operation, making it suitable for awide variety of RF and IF applications. Covering DCto 10 GHz, the insertion loss is less than 3 dB typicaland attenuation accuracy is excellent at ?0.6 dB typ-ical. The attenuator also features a high IIP3 of +55dBm. One TTL/CMOS control input is used to selectthe attenuation state and a single Vdd bias of +5V isrequired. Applications Test equipment and sensors ISM, MMDS, WLAN,?WiMAX, WiBro Microwave radio & VSAT Cellular infrastructure

DC1947A: Demo Board for the LT3799-1 Offline Isolated Flyback LED Controller with Active PFC.

The ADAR4002 is a very low power broadband bi-directional single channel true time delay unit (TDU) and a digital step attenuator (DSA). The IC has 18.5 GHz of bandwidth over a frequency range of 0.5 GHz to 19 GHz with 50 ? input impedance at both RF ports. The TDU has two programmable maximum time delays, each with 7-bit control: Range 0 has a maximum delay of 508ps with a resolution of 4ps. This range is used at lower frequencies and where the ADAR4002 has less loss. Range 1 has a maximum delay of 254ps and a resolution of 2ps. This range has less loss compared to Range 0 and is useful at higher frequencies. The DSA has 6-bit resolution with an attenuation range of 0 dB to 31.5 dB and a step size of 0.5 dB. The ADAR4002 is designed to provide flexible digital control through either a SPI interface or a shift register to allow daisy chaining multiple chips together. The ADAR4002 contains register memory for 32 TDU+DSA states. The memory combined with on-chip sequencers, allows a fast memory advance via the UPDATE pin.The ADAR4002 is available in a 2 mm ? 3 mm 14-lead LFCSP package and is specified from -40?C to 85?C.APPLICATIONSElectronic steerable antenna arraysMulti-Function ArraysSATCOMRADARData LinksTest Equipment

The ADP1754 /?ADP1755?are CMOS, low dropout linear regulators that operate from 1.6 V to 3.6 V and provide up to 1.2A of output current. These Low Vin?/ Vout LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5V down to 1.8V I/O rails, and powering core voltages down to 0.75V. Using an advanced proprietary architecture, they provide high power supply rejection, low noise, and achieve excellent line and load transient response with a small 4.7 ?F ceramic output capacitor.The ADP1754 is available in 7 fixed output voltage options. The ADP1755 is available in an adjustable version, which allows output voltages that range from 0.75 V to 3.0 V via an external divider. The ADP1754 / ADP1755 allows an external soft start capacitor to be connected to program the start-up. A power good output allows power system monitors to digitally check the health of the output power rail voltage.The ADP1754 / ADP1755 are available in a 16-lead, 4 mm ? 4 mm LFCSP, making them not only very compact solutions, but also providing excellent thermal performance for applications requiring up to 1.2A of output current in a small, low profile footprint.APPLICATIONS Server computers Memory components Telecommunications equipment Network equipment DSP/FPGA/microprocessor supplies Instrumentation equipment/data acquisition systems

Demonstration circuit 1516A is a 1.5V/15A synchronous buck converter operating with a switching frequency of 300kHz over an input voltage range of 4.5V to 24V. The demo board comes in two versions. The -A version uses inductor DCR current sensing with an iron powder inductor for highest efficiency. The -B version uses a 2.5mΩ/1% sense resistor for accurate current sensing with a low DCR ferrite inductor. The fixed on-time valley current mode control of the LTC3833 allows for a fast load step response.

DC1324A: Demo Board for LTC3672B-2 - Monolithic Fixed-Output 400mA Buck Regulator with Dual 150mA LDOs in 2mm × 2mm DFN

The HMC1082CHIP is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), driver amplifier that operates from 5.5 GHz to 18 GHz. The HMC1082CHIP provides a typical gain of 24 dB, 36 dBm output IP3, and 25.5 dBm of output power for 1 dB compression, requiring only 220 mA from a 5 V supply voltage. The saturated output power (PSAT) is 26 dBm with 24% power added efficiency (PAE).The HMC1082CHIP is an ideal driver amplifier for a wide range of applications including point to point radios from 5.5 GHz to 18 GHz and marine radars at 9 GHz. The HMC1082CHIP can also be used for 6 GHz to 18 GHz EW and ECM applications.APPLICATIONS Software defined radios Electronics warfare (EW) Radar applications Electronic countermeasures (ECMs)

The ADV8003 is a multiple input video signal processor that can de-interlace and scale SD, ED, or HD video data to HD formats, generate a bitmap on-screen display (OSD) and output the video with OSD overlaid on two High Definition Multimedia Interface (HDMI) transmitters and a video encoder.Video can be input into the ADV8003 in a number of ways: using the 48-bit TTL pixel port, using the 24-bit external OSD TTL pixel port, or from a device with a HDMI transmitter such as the ADV7850. The ADV8003 supports many of the formats outlined in the CEA-861 and VESA specifications, as well as several other widely used timing formats.Using two external DDR2 memories, the ADV8003 can perform high performance, motion adaptive interlaced to progressive conversion on SD and HD content. Using a single DDR2 memory, the HD de-interlacing is limited to intrafield.The ADV8003 features primary and secondary video scalers that enable simultaneous output of multiple different resolutions. Detail enhancement and image enhancing techniques such as random, mosquito, and block noise reduction allow for improved final image quality. The frame rate converter of the ADV8003 allows the conversion between common frame rates with support to output two different frame rates simultaneously under certain conditions.The ADV8003 has a flexible digital core that allows the user to configure the part in several different modes: using a single video processing channel, using dual video processing channels, or displaying OSD on multiple outputs of different resolutions. The ADV8003 can accept OSD information from either an external OSD source on the 24-bit external OSD TTL pixel data input or internally generate a high quality, bitmap-based OSD. The internal OSD is highly flexible and allows the system designer to easily incorporate features like scrolling text and animation in various color depths up to 24-bit true color.Analog Devices, Inc., provides an OSD development tool (Blimp) to assist in the design, debug, and emulation of the OSD prior to integration with the system application. When the design is complete, the OSD development tool automatically generates code to which system APIs can be added before integration with the system application and an OSD design resource, which must be downloaded to an external SPI flash memory.Video can be output from the ADV8003 using one or both of the HDMI transmitters and/or the 6-DAC SD/HD video encoder. The flexible multiplexing in the part allows simultaneous output of HD formats on the HDMI transmitters and on the HD DACs (for example, 1080p) with SD formats on the SD DACs (for example, 480i).Both of the HDMI transmitters on the ADV8003 support all mandatory and many optional 3D video resolutions and audio return channels (ARC). Each transmitter also features a full CEC master. The ADV8003 can receive up to six channels of I2S, S/PDIF, direct stream digital (DSD), and high bit rate (HBR). The six 12-bit NSV? video DACs allow for composite (CVBS), S-Video (Y/C), and component (YPrPb) analog outputs in standard, enhanced, and high definition video formats. Oversampling of 216 MHz (SD and ED) and 297 MHz (HD) removes the requirement for external output filtering.The ADV8003 can also support 30-bit TTL in and 30-bit TTL out mode for professional applications.The ADV8003 supports the I2C? protocol for communication with the system microcontroller.APPLICATIONS High end A/V receivers Upconverting DVD players/recorders Blu-ray players/recorders Set-top boxes Video conferencing Standalone video processors HDMI splitters

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment