DEM-SOT23LDO Compatible With Most Positive-Output LDO Regulators in 5- or 6-Lead SOT23 (DBV) Package

The LTC3882 is a dual, PolyPhase DC/DC synchronous step-down switching regulator controller with PMBus compliant serial interface. It uses a constant frequency, leading-edge modulation, voltage mode architecture for excellent transient response and output regulation. Each PWM channel can produce output voltages from 0.5V to 5.25V using a wide range of 3.3V compatible power stages, including power blocks, DrMOS or discrete FET drivers. Up to four LTC3882s can operate in parallel for 2-, 3-, 4-, 6- or 8-phase operation.LTC3882 system configuration and monitoring is supported by the LTpowerPlay? software tool. The device?s serial interface can be used to read back input voltage, output voltage and current, temperature and fault status. A wide range of operating parameters can be set via the digital interface or stored in internal EEPROM for use at power up. Switching frequency and phase, output voltage and device address can also be programmed using external configuration resistors. PWM?Enable Output TG/BG Control HW?Write Protect Dedicated PGOOD Differential Vout Sense LTC3882 Yes Yes Yes No? VOUT0 Only LTC3882-1 ?No No No Yes VOUT0 & VOUT1 Applications High Current Distributed Power Systems Servers, Network and Storage Equipment Intelligent Energy Efficient Power Regulation Industrial/Telecom/ATE Systems

EVAL BOARD FOR TPS563210

The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltagecomparators fabricated on the Analog Devices, Inc. proprietaryXFCB3 Silicon Germanium (SiGe) bipolar process. TheADCMP580 features CML output drivers, the ADCMP581features reduced swing ECL (negative ECL) output drivers, andthe ADCMP582 features reduced swing PECL (positive ECL)output drivers.All three comparators offer 180 ps propagation delay and 100 psminimum pulse width for 10 Gbps operation with 200 fs randomjitter (RJ). Overdrive and slew rate dispersion are typically lessthan 15 ps.The ?5 V power supplies enable a wide ?2 V to +3 V inputrange with logic levels referenced to the CML/NECL/PECLoutputs. The inputs have 50 ? on-chip termination resistorswith the optional capability to be left open (on an individualpin basis) for applications requiring high impedance input. The CML output stage is designed to directly drive 400 mV into50 ? transmission lines terminated to ground. The NECL outputstages are designed to directly drive 400 mV into 50 ? terminatedto ?2 V. The PECL output stages are designed to directly drive400 mV into 50 ? terminated to VCCO ? 2 V. High speed latchand programmable hysteresis are also provided. The differentiallatch input controls are also 50 ? terminated to an independentVTT pin to interface to either CML or ECL or to PECL logic.The ADCMP580/ADCMP581/ADCMP582 are available in a16-lead LFCSP.Applications Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration

BQ24120 Evaluation Module

DC2027A-B: Demo Board for the LTC4364 Surge Stopper with Ideal Diode.

LM3263EVM DC/DC Converter with MIPI® RFFE Interface Evaluation Module for RF Power Amplifiers

TSC2003EVM-PDK Evaluation Module

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Power Management IC Development Tools