The HMC881A is a monolithic microwave integrated circuit (MMIC) low-pass filter that features a user-selectable cutoff frequency. The cutoff frequency can be varied from 2.4 GHz to 4 GHz by applying a single analog tuning voltage between 0 V and 14 V. This low-pass filter provides a low 3 dB insertion loss, 16.5 dB return loss, and 1.35 ? f3dB stopband attenuation of >20 dB. This tunable filter can be used as a much smaller alternative to physically large switched filter banks and cavity tuned filters. The HMC881A has excellent microphonics due to the monolithic design, and provides a dynamically adjustable solution in advanced communications applications. The low-pass tunable filter is packaged in a RoHS compliant 5 mm ? 5 mm LFCSP package.Applications Testing and measurement equipment Military radar and electronic warfare/electronic countermeasures (ECMs) Satellite communication and space Industrial and medical equipment

The HMC892ALP5E is a tunable band-pass filter that features auser selectable pass-band frequency. The 3 dB filter bandwidth isapproximately 8.7%. The 20 dB filter bandwidth is approximately23.8%. The center frequency can be varied between 3.45 GHzand 6.25 GHz by applying an analog tuning voltage between 0 Vand 14 V.This tunable filter can be used as a smaller alternative tophysically large switched filter banks and cavity tuned filters.The HMC892ALP5E has excellent microphonics due to themonolithic design and provides a dynamically adjustablesolution in advanced communications applications. Applications Test and measurement equipment Military radar and electronic warfare (EW)/electronic countermeasures (ECM) Satellite communications (SATCOM) and space Industrial and medical equipment

The HMC908A is a compact, gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), inphase/quadrature (I/Q) downconverter in a leadless, RoHS compliant ceramic leadless chip carrier. This device provides a small signal conversion gain of 11 dB with a noise figure of 2 dB and 25 dB of image rejection at 100 MHz. The HMC908A utilizes a low noise amplifier (LNA) followed by an image rejection mixer that is driven by a local oscillator (LO) buffer amplifier. The image rejection mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC908A is a much smaller alternative to hybrid style image rejection mixer downconverter assemblies, and it eliminates the need for wire bonding by allowing the use of surface-mount manufacturing techniques.Applications Point to point radios Point to multipoint radios and very small aperture terminals (VSATs) Test equipment and sensors Military end use

The EV-ADE9153ASHIELDZ is an Arduino shield compatible with Arduino Uno, Arduino Zero, or ESP8266. The shield has an on-board shunt resistor for line current measurement and enables quick evaluation and prototyping of energy measurement systems that use the ADE9153A. Arduino library and application examples are provided on the ADE9153A product page to simplify implementation of larger systems. Using mSure® autocalibration, the shield can be calibrated to measure energy with 1% accuracy over the dynamic range without the need for expensive calibration equipment.

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture isspecifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes theADF4196 suitable for pulse Doppler radar applications.The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (?-?) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Pulsed Doppler radar Instrumentation and test equipment Beam-forming/phased array systems

The ADF4355 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers permits operation from 54 MHz to 6800 MHz.The ADF4355 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate radio frequency (RF) output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4355 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4355 also contains hardware and software power-down modes.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The ADF4360-3 is a fully integrated integer-N synthesizer andvoltage controlled oscillator (VCO). The ADF4360-3 is designedfor a center frequency of 1750 MHz. In addition, there is adivide-by-2 option available, whereby the user gets an RF output of between 800 MHz and 975 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.?

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of ?20 dBm to +13 dBm and ?20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM??Cortex?-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the?IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm ? 6 mm, 40-lead LFCSP and a 7 mm ? 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is ?40?C to +85?C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_CON is a programmable value that configures the internal LDO voltage that provides bias for the PA. For additional information on these bit settings, see the ADF7030-1 Software Reference Manual, which is the detailed programming guide for the device.Applications IEEE 802.15.4g (MR-FSK PHY)? Wireless M-Bus (EN 13757-4) Smart metering Security and building automation? Active tag asset tracking Industrial control Wireless sensor networks (WSNs)

The ADuCM322 is a fully integrated, single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM? Cortex?-M3 processor and integral flash for code and data.The ADC on the ADuCM322 provides 12-bit, 1 MSPS data acquisition on up to 16 input balls. Additionally, chip temperature and supply voltages can be measured.The ADC input voltage range is 0 V to VREF. A sequencer is provided, which allows a user to select a set of ADC channels to measure in sequence without software involvement during the sequence. The sequence can optionally repeat automatically at a user selectable rate. Up to eight VDACs are provided with output ranges that are programmable to one of two voltage ranges.The ADuCM322 can be configured so that the digital and analog outputs retain their output voltages through a watchdog or software reset sequence. Thus, a product can remain functional even while the ADuCM322 is resetting itself.The ADuCM322 has a low power ARM Cortex-M3 processor and a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on-chip are 2 ? 128 kB Flash/EE memory blocks and 32 kB of SRAM. The flash comprises two separate 128 kB blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block.The ADuCM322 operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In normal operating mode, the ADuCM322 digital core consumes about 300 ?A per MHz.The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADuCM322 ideal for 10G, 40G, and 100G optical applications. In addition, the nonerasable kernel code plus flags in user flash provide assistance by allowing user code to robustly switch between the two blocks of user flash code and data spaces.The ADuCM322 integrates a range of on-chip peripherals that can be configured under software control, as required in the application. These peripherals include 1 ? UART, 2 ? I2C, and 2 ? SPI serial input/output communication controllers, GPIO, 32-element PLA, three general-purpose timers, plus a wake-up timer and system watchdog timer. A 16-bit PWM with seven output channels is also provided.GPIO balls on the device power up in high impedance input mode. In output mode, the software chooses between open-drain mode and push-pull mode. The pull-up resistors can be disabled and enabled in software. In GPIO output mode, the inputs can remain enabled to monitor the balls. The GPIO balls can also be programmed to handle digital or analog peripheral signals; in such cases, the ball characteristics are matched to the specific requirement.A large support ecosystem is available for the ARM Cortex-M3 processor to ease product development of the ADuCM322. Access is via the ARM serial wire debug port (SW-DP). On-chip factory firmware supports in-circuit serial download via MDIO. These features are incorporated into a QuickStart? development system, supporting this precision analog microcontroller family.APPLICATIONS Optical networking