The LTC4066/LTC4066-1 are USB power managers and Li-Ion battery chargers designed to work in portable battery-powered applications. The parts control the total current used by the USB peripheral for operation and battery charging. The total input current can be limited to 100mA, 500mA or ?unlimited? (i.e., above 2A). Battery charge current is automatically reduced such that the sum of the load current and the charge current does not exceed the programmed input current limit.The LTC4066/LTC4066-1 include a standalone constant-current / constant-voltage linear charger for single cell Li-ion batteries. The ?oat voltage applied to the battery is held to a tight 0.8% tolerance, and charge current is programmable using an external resistor to ground. A programmable end-of-charge status output (CHRG) indicates full charge. BAT pin charge and discharge currents can be monitored via an analog output (ISTAT). Total charge time is programmable by an external capacitor to ground. When the battery drops 100mV below the ?oat voltage, automatic recharging of the battery occurs. Also featured is an NTC thermistor input used to monitor battery temperature while charging.The LTC4066/LTC4066-1 are available in a 24-pin thin pro?le (0.75mm) 4mm x 4mm QFN package. The LTC4066 is also available in a 24-pin ultrathin pro?le (0.55mm) 4mm x 4mm UTQFN package.Applications Portable USB Devices GPS, Cameras, Broadband Wireless Modems Mulitple Input Chargers

The LT5506 is a 40MHz to 500MHz monolithic integrated quadrature demodulator with variable gain amplifier (VGA), designed for low voltage operation. It supports standards that use a linear modulation format. The chip consists of a VGA, quadrature down-converting mixers and lowpass noise filters. The LO port consists of a divide-by-two stage and LO buffers. The IC provides all building blocks for IF down-conversion to I and Q baseband signals with a single supply voltage of 1.8V to 5.25V. The VGA gain has a linear-in- dB relationship to the control input voltage. Hard-clipping amplifiers at the mixer outputs reduce the recovery time from a signal overload condition. The lowpass filters reduce the out-of-band noise and spurious frequency components. The cut-off frequency of the noise filters is approximately 8.8MHz. The external 2xLO frequency is required to be twice the IF input frequency for the mixers. The standby mode provides reduced supply current and fast transient response into the normal operating mode when the I/Q outputs are AC-coupled to a baseband chip.Applications IEEE802.11 High Speed Wireless LAN Wireless Local Loop

The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) forsignaling a new output byte are provided. Individual channelpower-down is supported; the AD9635 typically consumes lessthan 2 mW in the full power-down state. The ADC providesseveral features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9635 is available in a RoHS-compliant, 32-lead LFCSP. It is specified over the industrial temperature range of ?40?Cto +85?C. PRODUCT HIGHLIGHTS Small Footprint. Two ADCs are contained in a small, spacesaving package. Low Power. The AD9635 uses 115 mW/channel at 125 MSPS with scalable power options. Pin Compatibility with the AD9645, a 14-Bit Dual ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand held scope meters Portable medical imaging and ultrasound Radar/LIDAR

The HMC539ALP3/539ALP3E is a broadband5-bit GaAs IC digital attenuator in a low cost leadless surface mount package. This single positive control line per bit digital attenuator utilizes an offchip AC ground capacitor for near DC operation,making it suitable for a wide variety of RF and IFapplications. Covering DC to 4 GHz, the insertion loss is less than 0.7 dB typical. The attenuatorbit values are 0.25 (LSB), 0.5, 1, 2, and 4 dB for atotal attenuation of 7.75 dB. Attenuation accuracy isexcellent at ? 0.05 dB typical step error. The attenu-ator also features a high IIP3 of +62 dBm. Five TTL/CMOS control inputs are used to select each attenuation state. A single Vdd bias of +3V to +5V is required.Applications Cellular infrastructure ISM, MMDS, WLAN, WiMAX, WiBro Microwave radio and VSAT Test equipment and sensors

The LT3585 series are highly integrated ICs designed to charge photo?ash capacitors in digital and ?lm cameras. A new control technique allows for the use of extremely small transformers. Each part contains an on-chip high voltage NPN power switch. Output voltage detection is completely contained within the part, eliminating the need for any discrete zener diodes or resistors. The output voltage can be adjusted by simply changing the turns ratio of the transformer.The CHRG/IADJ pin gives full control of the part to the user. Driving CHRG/IADJ low puts the part in low power shutdown. The CHRG/IADJ pin can also be used to reduce the input current of the charger, useful in extending battery life. The DONE pin indicates when the part has completed charging.The LT3585 series of parts are housed in tiny 3mm ? 2mm DFN packages.Applications Digital/Film Camera Flash PDA/Cell Phone Flash Emergency Strobe

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The HMC8205BF10 is a gallium nitride (GaN) broadband power amplifier delivering 45.5 dBm (35 W) with 38% power added efficiency (PAE) across an instantaneous bandwidth of 0.3 GHz to 6 GHz. No external matching is required to achieve full band operation. Additionally, no external inductor is required to bias the amplifier. Also, dc blocking capacitors for the RFIN and RFOUT pins are integrated into the HMC8205BF10.The HMC8205BF10 is ideal for pulsed or continuous wave(CW) applications, such as military jammers, wirelessinfrastructure, radar, and general-purpose amplification.The HMC8205BF10 amplifier is a 10-lead ceramic leaded chip carrier (LDCC).The HMC8205BCHIPS is a gallium nitride (GaN), broadbandpower amplifier that delivers 45.5 dBm (35 W) with 40% poweradded efficiency (PAE) across an instantaneous bandwidth of0.4 GHz to 6 GHz. No external matching is required to achievefull band operation. No external inductor is required to bias theamplifier. In addition, dc blocking capacitors for the RFIN andRFOUT pins are integrated into the HMC8205BCHIPS.The HMC8205BCHIPS is ideal for pulsed or continuous wave(CW) applications, such as military jammers, wirelessinfrastructure, radar, and general-purpose amplification.APPLICATIONS Military jammers Commercial and military radar Power amplifier stage for wireless infrastructure? Test and measurement equipment

The HMC7357 is a three-stage GaAs pHEMT MMIC Medium Power Amplifier that operates between 5.5 and 8.5 GHz. The amplifier provides 29 dB of gain and +35 dBm of saturated output power at 34% PAE from a +8V supply. With an excellent Output IP3 of +41.5 dBm, the HMC7357 is ideal for linear applications such as high capacity point-to-point and point-to-multi-point radios or VSAT/SATCOM applications demanding +35 dBm of efficient saturated output power. The RF I/Os are internally matched to 50 Ohms for ease of use. The HMC7357 is packaged in a leadless 5x5 mm plastic surface mount package and is compatible with surface mount manufacturing techniques.Applications Point-to-Point Radios Point-to-Multi-Point Radios VSAT & SATCOM

DC782A-Q: Demo Board for the LTC2249 14-Bit, 80Msps Low Power 3V ADC.

The ADG1634L is a monolithic industrial CMOS (iCMOS?) analog switch comprising four independently selectable single-pole, double-throw (SPDT) switches, respectively.All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG1634L is used to enable or disable the device. When disabled, all channels are switched off. The switch is enabled with a Logic 1 EN input, while the INx input defines the state of the SPDT switch (see Table 12 in the data sheet).The ultralow on resistance and on-resistance flatness of the switch makes it an ideal solution for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultra low power dissipation, making the device ideally suited for portable and battery-powered instruments.An external VL supply provides flexibility for lower logic control. The ADG1634L is both 1.2 V and 1.8 V JEDEC standard compliant.APPLICATIONS Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems FPGA and microcontroller systems Sample-and-hold systems Relay replacementsPRODUCT HIGHLIGHTS 8.2 ? maximum on resistance over temperature. Minimum distortion. VL supply for low logic level compatibility. JEDEC standard compliant for both 1.2 V and 1.8 V logic levels. Guaranteed switch off when digital inputs are floating. 24-lead, 4 mm ? 4 mm LFCSP.