The LT1965 series are low noise, low dropout linear regulators. The devices supply 1.1A of output current with a 310mV typical dropout voltage. Operating quiescent current is 500?A for the adjustable version, reducing to <1?A in shutdown. Quiescent current is well controlled; it does not rise in dropout as with many other regulators. The LT1965 regulators have very low output noise which makes them ideal for sensitive RF and DSP supply applications.Output voltage ranges from 1.20V to 19.5V. The LT1965 regulators are stable with output capacitors as low as 10?F. Internal protection circuitry includes reverse-battery protection, current limiting with foldback, thermal limiting and reverse-current protection. The LT1965 series are available in fixed output voltages of 1.5V, 1.8V, 2.5V, 3.3V, and as an adjustable device with a 1.20V reference voltage. The package offerings include the 5-lead TO-220, 5-lead DD-Pak as well as the thermally enhanced 8-lead MSOP and low profile (0.75mm) 8-lead 3mm ? 3mm DFN.Applications Logic Power Supplies Post Regulator for Switching Supplies Low Noise Instrumentation

The LTC6363 family consists of four fully differential, low power, low noise amplifiers with rail-to-rail outputs optimized to drive SAR ADCs. The LTC6363 is a standalone differential amplifier, where the gain is typically set using four external resistors. The LTC6363-0.5, LTC6363-1, and LTC6363-2 each have internal matched resistors to create fixed gain blocks with gains of 0.5V/V, 1V/V, and 2V/V respectively. Each of the fixed-gain amplifiers features precision laser trimmed on-chip resistors for accurate, ultrastable gain and excellent CMRR.Applications 20-Bit, 18-Bit and 16-Bit SAR ADC Drivers Single-Ended-to-Differential Conversion Low Power ADC Drivers Level Shifter Differential Line Drivers Battery-Powered Instrumentation

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm ? 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.Applications Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

Demonstration circuit 2898A is a dual DC/DC converter with a 13V to 40V input voltage range, two 12V outputs at 4A each featuring the LTM4655. The LTM4655 is a EN55022B compliant 40V, dual 4A or single 8A step-down or 50W inverting DC/DC μModule® regulator. The switching frequencies of both channels are set at 1.2MHz on DC2898A. If the output voltage collapses sufficiently due to an overload or short-circuit condition, the internal oscillator will foldback to one-fifth of the LTM4655’s programmed switching frequency, protecting the power switch from damage. Key features of this board include: SSFM Jumper for Spread Spectrum Options CLKIN Inputs for External Sync PGOOD Signals for Each Output The two channels can be paralleled for higher output current. See the data sheet for more information on setting up the board for paralleling the two outputs. The LTM4655 data sheet gives a complete description of the device, its operation and application information. The data sheet must be read in conjunction with the demo manual prior to working on or modifying DC2898A.

DC929A-B: Demo Board for the LTC4089 USB Power Manager with High Voltage Switching Charger.

The ADCLK905 (one input, one output), ADCLK907 (dual oneinput, one output), and ADCLK925 (one input, two outputs) areultrafast clock/data buffers fabricated on the Analog Devices, Inc.,proprietary XFCB3 silicon germanium (SiGe) bipolar process.The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).The inputs have center tapped, 100 ?, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.Applications Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking

Demonstration circuit DC2343A is a complete system level solution for a nanopower buck-boost DC/DC with integrated coulomb counter. The DC2343A contains a PIC16F1459 embedded processor for communication to the PC over USB and the LTC3335 via its I2C port. The GUI is capable of reading and writing all the control registers on the LTC3335 as well as displaying and resetting all its alarm registers. The firmware and software for the embedded system and the GUI are available at the LTC3335 solutions page. The DC2343A uses two analog-to-digital converter channels to sample the battery and output voltages. The voltage samples improve the functionality of the GUI, and allow optimal software correction to the measured coulombs. By adding the software correction the first order known errors are compensated for over the operating range and the resultant coulomb count is accurate to within 3%.

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells? FDD and TDD active antenna systems? Microwave, nonline of sight (NLOS) backhaul systems

The LTM4632 is an ultrathin triple output step-down ?Module? (power module) regulator to provide complete power solution for DDR-QDR4 SRAM. Operating from a 3.6V to 15V input voltage, the LTM4632 supports two ?3A output rails, both sink and source capable, for VDDQ and VTT, plus a 10mA low noise reference VTTR output. Both VTT and VTTR track and are equal to VDDQ/2. Housed in a 6.25mm ? 6.25mm ? 1.82mm LGA and 6.25mm ? 6.25mm ? 2.42mm BGA packages, the LTM4632 includes the switching controller, power FETs, inductors and support components. Alternatively, the power module can also be configured as a two phase single ?6A output VTT. Only a few ceramic input and output capacitors are needed to complete the design.The LTM4632 supports selectable Burst Mode operation (CH1 only) and output voltage tracking for supply rail sequencing. Its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability.Fault protection features include overvoltage input, overcurrent and overtemperature protection.The LTM4632 is RoHS compliant with Pb-free finish.Applications DDR Memory Power Supply General Purpose Point of Load Conversion Telecom, Networking and Industrial Equipment

The HMC374(E) is a general purpose broad band Low Noise Amplifier (LNA) for use in the 0.3 - 3.0 GHz frequency range. The LNA provides 15 dB of gain and a 1.5 dB noise figure from a single positive supply of +2.75 to +5.5V. The low noise figure coupled with a high P1dB (22 dBm) and high OIP3 (37 dBm) make this part ideal for cellular applications. The compact LNA design utilizes on-chip matching for repeatable gain and noise figure performance. To minimize board area the design is offered in a low cost SOT26 package that occupies only 0.118? x 0.118?.Applications Cellular/PCS/3G? WCS, MMDS & ISM? Fixed Wireless & WLAN? Private Land Mobile Radio