DC1324A: Demo Board for LTC3672B-2 - Monolithic Fixed-Output 400mA Buck Regulator with Dual 150mA LDOs in 2mm × 2mm DFN

The HMC1082CHIP is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), driver amplifier that operates from 5.5 GHz to 18 GHz. The HMC1082CHIP provides a typical gain of 24 dB, 36 dBm output IP3, and 25.5 dBm of output power for 1 dB compression, requiring only 220 mA from a 5 V supply voltage. The saturated output power (PSAT) is 26 dBm with 24% power added efficiency (PAE).The HMC1082CHIP is an ideal driver amplifier for a wide range of applications including point to point radios from 5.5 GHz to 18 GHz and marine radars at 9 GHz. The HMC1082CHIP can also be used for 6 GHz to 18 GHz EW and ECM applications.APPLICATIONS Software defined radios Electronics warfare (EW) Radar applications Electronic countermeasures (ECMs)

The ADV8003 is a multiple input video signal processor that can de-interlace and scale SD, ED, or HD video data to HD formats, generate a bitmap on-screen display (OSD) and output the video with OSD overlaid on two High Definition Multimedia Interface (HDMI) transmitters and a video encoder.Video can be input into the ADV8003 in a number of ways: using the 48-bit TTL pixel port, using the 24-bit external OSD TTL pixel port, or from a device with a HDMI transmitter such as the ADV7850. The ADV8003 supports many of the formats outlined in the CEA-861 and VESA specifications, as well as several other widely used timing formats.Using two external DDR2 memories, the ADV8003 can perform high performance, motion adaptive interlaced to progressive conversion on SD and HD content. Using a single DDR2 memory, the HD de-interlacing is limited to intrafield.The ADV8003 features primary and secondary video scalers that enable simultaneous output of multiple different resolutions. Detail enhancement and image enhancing techniques such as random, mosquito, and block noise reduction allow for improved final image quality. The frame rate converter of the ADV8003 allows the conversion between common frame rates with support to output two different frame rates simultaneously under certain conditions.The ADV8003 has a flexible digital core that allows the user to configure the part in several different modes: using a single video processing channel, using dual video processing channels, or displaying OSD on multiple outputs of different resolutions. The ADV8003 can accept OSD information from either an external OSD source on the 24-bit external OSD TTL pixel data input or internally generate a high quality, bitmap-based OSD. The internal OSD is highly flexible and allows the system designer to easily incorporate features like scrolling text and animation in various color depths up to 24-bit true color.Analog Devices, Inc., provides an OSD development tool (Blimp) to assist in the design, debug, and emulation of the OSD prior to integration with the system application. When the design is complete, the OSD development tool automatically generates code to which system APIs can be added before integration with the system application and an OSD design resource, which must be downloaded to an external SPI flash memory.Video can be output from the ADV8003 using one or both of the HDMI transmitters and/or the 6-DAC SD/HD video encoder. The flexible multiplexing in the part allows simultaneous output of HD formats on the HDMI transmitters and on the HD DACs (for example, 1080p) with SD formats on the SD DACs (for example, 480i).Both of the HDMI transmitters on the ADV8003 support all mandatory and many optional 3D video resolutions and audio return channels (ARC). Each transmitter also features a full CEC master. The ADV8003 can receive up to six channels of I2S, S/PDIF, direct stream digital (DSD), and high bit rate (HBR). The six 12-bit NSV? video DACs allow for composite (CVBS), S-Video (Y/C), and component (YPrPb) analog outputs in standard, enhanced, and high definition video formats. Oversampling of 216 MHz (SD and ED) and 297 MHz (HD) removes the requirement for external output filtering.The ADV8003 can also support 30-bit TTL in and 30-bit TTL out mode for professional applications.The ADV8003 supports the I2C? protocol for communication with the system microcontroller.APPLICATIONS High end A/V receivers Upconverting DVD players/recorders Blu-ray players/recorders Set-top boxes Video conferencing Standalone video processors HDMI splitters

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The LTM4681 is a quad 31.25A or single 125A stepdown??Module? (power module) DC/DC regulator featuring?remote configurability and telemetry-monitoring?of power management parameters over PMBus. The?LTM4681 is comprised of digitally programmable analog?control loops, precision mixed-signal circuitry, EEPROM,?power MOSFETs, inductors and supporting components.The LTM4681?s 2-wire serial interface allows outputs?to be margined, tuned and ramped up and down at programmable?slew rates with sequencing delay times. True input current sense, output currents and voltages, output?power, temperatures, uptime and peak values are readable. Custom configuration of the EEPROM contents is not?required. At start-up, output voltages, switching frequency,?and channel phase angle assignments can be set by pinstrapping?resistors. The LTpowerPlay? GUI and DC1613?USB-to-PMBus converter and demo kits are available.?The LTM4681 is offered in a 15mm ? 22mm ? 8.17mm?BGA package available with SnPb or RoHS compliant?terminal finish.APPLICATIONS Multi-Rail Processor Power, Configurable Core Power

The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.6 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures.The analog input, clock, and SYSREF? signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference. Flexible digital data output formats based on the JESD204B specification. Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values.APPLICATIONS Spectrum analyzers Military communications Radar High performance digital storage oscilloscopes Active jamming/antijamming Electronic surveillance and countermeasures

The analog output ADXL354 and the digital output ADXL355 are low noise density, low 0 g offset drift, low power, 3-axisaccelerometers with selectable measurement ranges. TheADXL354B supports the ?2 g and ?4 g ranges, the ADXL354Csupports the ?2 g and ?8 g ranges, and the ADXL355 supports the ?2 g, ?4 g, and ?8 g ranges. The ADXL354/ADXL355 offerindustry leading noise, minimal offset drift over temperature,and long-term stability enabling precision applications with minimal calibration.Highly integrated in a compact form factor, the low powerADXL355 is ideal in an Internet of Things (IoT) sensor nodeand other wireless product designs.The ADXL355 multifunction pin names may be referenced by their relevant function only for either the serial peripheralinterface (SPI) or I2C interface.Applications Inertial measurement units (IMUs)/altitude and heading reference systems (AHRS) Platform stabilization systems Structural health monitoring Seismic imaging Tilt sensing Robotics Condition Monitoring

The Analog Devices, Inc., amplifier mezzanine card (AMC) analog-to-digital converter (ADC) driver evaluates the performance of amplifiers in 8-lead, single and dual SOIC, 6-lead single SOT23, 8-lead dual MSOP, and 16-lead LFCSP packages. This add on board can be inserted on ADC evaluation boards using its 7-pin header. Figure 1 shows the AMC mounted on an Analog Devices, Inc., ADC evaluation board. The AMC can support any of Analog Devices operational amplifiers and ADC drivers in different packages. The user can configure the ADC driver as a Sallen-Key low-pass, high-pass, or band-pass filter, as a multiple feedback low-pass, high-pass, or band-pass filter, or as an inverting and noninverting operational amplifier. The user can also configure the AMC to drive a single-ended, fully differential, or a single-ended signal to a differential ADC. Optimized power and ground planes ensure low noise and high speed operation. Component placement and power supply bypassing are optimized for maximum circuit flexibility and performance. The AMC evaluation board accepts 0402 or 0603 surface mount technology (SMT) components, 1206 bypass capacitors, and 2.54 mm headers. All components are placed on the primary side. No components are placed on the secondary side.

The ADXL363 is an ultralow power, three-sensor combination consisting of a 3-axis MEMS accelerometer, a temperature sensor, and an on-board analog-to-digital converter (ADC) input for synchronous conversion of an external signal. The entire system consumes less than 2 ?A at a 100 Hz output data rate and 270 nA when in motion triggered wake-up mode.The ADXL363 communicates via a serial port interface (SPI) and always provides 12-bit output resolution for all three sensors.The ADXL363 temperature sensor operates with a scale factor of 0.065?C/LSB (typical). Acceleration and temperature data can be stored in a 512-sample multimode first in, first out (FIFO) buffer, allowing up to 13 sec of data to be stored.In addition to the accelerometer and temperature sensor, the ADXL363 also provides access to an internal ADC for synchronous conversion of an additional analog input.The ADXL363 operates on a wide 1.6 V to 3.5 V supply range, and can interface, if necessary, to a host operating on a separate, lower supply voltage. The ADXL363 is available in a 3 mm ? 3.25 mm ? 1.06 mm package.APPLICATIONS Home healthcare devices Wireless sensors Motion enabled metering devices