The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power?Consumes only 410 mW @ 300 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?12-bit pin-compatible family offered as AD9230.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.?The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.Product Highlights Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

DC1251A-B: Demo Board for LTC6601-2 - Low Power, Low Distortion, Low Power, Low Distortion, 5MHz to 27MHz, Pin Configurable Filter/ADC Driver

The LTC1605 is a 100ksps, sampling 16-bit A/D converter that draws only 55mW (typical) from a single 5V supply. This easy-to-use device includes sample-and-hold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock.The LTC1605?s input range is an industry standard ?10V. Maximum DC specs include ?2.0LSB INL and 16-bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed.The ADC has a microprocessor compatible, 16-bit or two byte parallel output port. A convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. Input Voltage Range LTC1605 Bipolar ?10V LTC1605-1 Unipolar 0V to 4V LTC1605-2 Bipolar ?4V Applications Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing

DC1266A-A: Demo Board for the LTC2453 Ultra-Tiny, Differential, 16-Bit ∆Σ ADC With I2C Interface

Demonstration circuit 1267A is a step-up DC/DC regulator featuring the LTC3125EDCB and is ideally suited for pulsed load applications where the input current needs to be limited. Demonstration circuit 1267A is configured for 500mA maximum input current limit and can handle pulsed load currents of up to 2A, with duty cycles of up to 15%. The input voltage range is 3.3V ±10%.

The LTC1520 is a high speed, precision differential line receiver that can operate at data rates as high as 50Mbps. A unique architecture provides very stable propagation delays and low skew over a wide input common mode, input overdrive and ambient temperature range. Propagation delay is 18ns ?3ns, while typically tPLH/tPHL skew is 500ps and channel-to-channel skew is 400ps.Each receiver translates differential input levels (VID ? 100mV) into valid CMOS and TTL output levels. Its high input resistance (?18k) allows many receivers to be connected to the same driver. The receiver outputs go into a high impedance state when disabled.Protection features include thermal shutdown and a controlled maximum short-circuit current (50mA max) that does not oscillate in and out of short-circuit mode. Input resistance remains ?18k when the device is unpowered or disabled, thus allowing the LTC1520 to be hot swapped into a backplane without loading the data lines.The LTC1520 operates from a single 5V supply and draws 12mA of supply current. The part is available in a 16-lead narrow SO package.Applications High Speed Backplane Interface Line Collision Detector PECL and LVDS Line Receivers Level Translator Ring Oscillator Tapped Delay Line

DC1273A: Demo Board for LT1938 - 25V, 2.2A, 2.8MHz Step-Down Switching Regulator

Demonstration circuit DC1297B features the LTM4612EV, an EN55022 Class B certified synchronous step-down power module. The board accepts an input voltage from 5V to 36V and delivers a jumper programmable output voltage of 3.3V, 5V or 12V. The rated load current is 5A for 3.3V and 5V output voltages, or 3A for a 12V output. Current derating is necessary for certain VIN, VOUT, and thermal conditions.