The ADP122 /?ADP123 are low quiescent current, low dropoutlinear regulators. They are designed to operate from an inputvoltage between 2.3 V and 5.5 V and to provide up to 300 mA of output current. The low 85 mV dropout voltage at a 300 mA loadimproves efficiency and allows operation over a wide inputvoltage range.The low 170 ?A of quiescent current at full load makes the ADP122ideal for battery-operated portable equipment.The ADP122 is capable of 31 fixed output voltages from 1.75 Vto 3.3 V. The ADP123 is the adjustable version of the device andallows the output voltage to be set between 0.8 V and 5.0 V by an external voltage divider.The ADP122 / ADP123 are specifically designed for stable operationwith tiny 1 ?F ceramic input and output capacitors to meet therequirements of high performance, space constrained applications.The ADP122 / ADP123 have an internal soft start that gives aconstant start-up time of 350 ?s. Short-circuit protection andthermal overload protection circuits prevent damage in adverse conditions. The ADP122 / ADP123 are available in a tiny, 5-leadTSOT package and 6-lead LFCSP package for the smallestfootprint solution to meet a variety of portable applications.APPLICATIONS Digital camera and audio devices Portable and battery-powered equipment Automatic meter reading (AMR) meters GPS and location management units Medical instrumentation Point-of-sale equipment

Demonstration circuit 1352A is a low quiescent current, dual output 2-phase, synchronous buck converter demo board featuring the LTC3857EGN-1 or LTC3858EGN-1. It features a 4.5V to 36V input voltage range and provides 3.3V / 5A and 8.5V / 3A outputs. Two versions of the board are available. The DC-1352A-A is for the LTC3857EGN-1, which offers lower quiescent current and smaller burst mode ripple, while the DC1352A-B is for the LTC3858EGN-1 which offers latch-off protection and increased burst mode efficiency.

Demonstration circuit DC1297B features the LTM4612EV, an EN55022 Class B certified synchronous step-down power module. The board accepts an input voltage from 5V to 36V and delivers a jumper programmable output voltage of 3.3V, 5V or 12V. The rated load current is 5A for 3.3V and 5V output voltages, or 3A for a 12V output. Current derating is necessary for certain VIN, VOUT, and thermal conditions.

Demonstration circuit SCP-LT3483-EVALZ is an inverting converter featuring the LT3483ES6. The converter generates –15V at 8mA to 40mA from a 2.7–12V input using a dual coupled inductor in an inverting flyback topology. Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely: SCP-INPUT-EVALZ SCP-OUTPUT-EVALZ SCP-1X5BKOUT-EVALZ SCP-THRUBRD-EVALZ SCP-FILTER-EVALZ SCP-1X2BKOUT-EVALZ SCP-5X1-EVALZ   To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and to-pology for your design. Note that the Demo Manual does not cover details important to the operation and configuration regarding the LT3483 buck regulator. Please refer to the LT3483 data sheet for a complete description of the part.

Demonstration circuit 806A features the LTC1867 Octal 16-bit ADC. The LTC1867 can be software programmed for a unipolar 0V to 4.096V or bipolar ±2.048V input range. The 8 channel multiplexer can be programmed for 8 single-ended inputs with respect to ground, 7 single-ended inputs with respect to the COM/CH7 pin, 4 differential inputs, or any combination of these.

The LTC6363 family consists of four fully differential, low power, low noise amplifiers with rail-to-rail outputs optimized to drive SAR ADCs. The LTC6363 is a standalone differential amplifier, where the gain is typically set using four external resistors. The LTC6363-0.5, LTC6363-1, and LTC6363-2 each have internal matched resistors to create fixed gain blocks with gains of 0.5V/V, 1V/V, and 2V/V respectively. Each of the fixed-gain amplifiers features precision laser trimmed on-chip resistors for accurate, ultrastable gain and excellent CMRR.Applications 20-Bit, 18-Bit and 16-Bit SAR ADC Drivers Single-Ended-to-Differential Conversion Low Power ADC Drivers Level Shifter Differential Line Drivers Battery-Powered Instrumentation

DC1094A: Demo Board for LTC4095 Standalone USB Li-Ion/Polymer Battery Charger in 2mm x 2mm DFN

Demonstration circuit SCP-LT1956-IEVALZ is a 48V, 1.5A buck regulator configured as an inverting buck topology for positive to negative DC voltage conversion. This board has ample current output to drive multiple signal chains. Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely: SCP-INPUT-EVALZ SCP-OUTPUT-EVALZ SCP-1X5BKOUT-EVALZ SCP-THRUBRD-EVALZ SCP-FILTER-EVALZ SCP-1X2BKOUT-EVALZ SCP-5X1-EVALZ   To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design. Note that this Demo Manual does not cover details important to the operation and configuration regarding the LT1956. Please refer to the LT1956 datasheet for a complete description of the part.

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations