The LTC1604 is a 333ksps, 16-bit sampling A/D converter that draws only 220mW from ?5V supplies. This high performance device includes a high dynamic range sample-and-hold, a precision reference and a high speed parallel output. Two digitally selectable power shutdown modes provide power savings for low power systems.The LTC1604's full-scale input range is ?2.5V. Outstanding AC performance includes 90dB S/(N+D) and ?100dB THD at a sample rate of 333ksps.The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15MHz bandwidth. The 68dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source.The ADC has ?P compatible,16-bit parallel output port. There is no pipeline delay in conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FlFOs, DSPs and microprocessors.Applications Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems

Demonstration circuit 2046A-E is a PoE powered device (PD) with an isolated power supply using synchronous flyback topology, featuring the LT4276 and ideal diode bridge controller (LT4321).

Demonstration circuit 761 is a low noise regulated charge pump featuring the LTC3204 (Burst Mode operation) in the 2 × 2 DFN package. There are two assembly versions, DC761A-A and DC761A-B for the LTC3204-5 (5V output) and LTC3204-3.3 (3.3V output) respectively. The DC761A-B produces a regulated 3.3V output from a 1.8V to 4.5V input. The guaranteed output current is 50mA from VIN between 1.9V and 4.5V, and 40mA for VIN less than 1.9V. The circuit requires only three tiny 0603 surface mount capacitors and uses minimal board space. No inductor or diodes are needed. The circuit features automatic Burst Mode® operation at light loads to maintain low supply current.

The ADP5053 combines four high performance buck regulators, a supervisory circuit, a watchdog timer, and a manual reset in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15.0 V with no preregulators.Channel 1 and Channel 2 integrate high-side power MOSFET and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration can provide a single output with up to 8 A of current.Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver an output current of 1.2 A.The switching frequency of the ADP5053 can be programmed or synchronized to an external clock. The ADP5053 contains a precision enable pin on each channel for easy power-up sequencing or adjustable UVLO threshold.The ADP5053 contains supervisory circuits that monitor the voltage level. The watchdog timer can generate a reset if the WDI pin is not toggled within a preset timeout period. Processor reset mode or system power on/off switch mode can be selected for manual reset functionality.Applications Small cell base stations FPGA and processor applications Security and surveillance Medical applications

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm ? 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.Applications Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

DC1082A-D: Demo Board for the LTC1403A Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown.

The ADGM1001/ADGM1002/ADGM1003 is a wideband, single-pole, two-throw (SP2T) switch, fabricated using Analog Devices, Inc., micro-electromechanical system (MEMS) switch technology. This technology enables a small form factor, wide RF bandwidth, highly linear, low insertion loss switch that is operational down to 0 Hz/dc, making it an ideal solution for a wide range of RF and precision equipment switching needs. The device is packaged in a 24-lead, 5.00 mm ? 4.00 mm ? 0.90 mm, land grid array (LGA) package.An integrated control chip generates the high voltage necessary to electrostatically actuate the switch via a complementary metal-oxide semiconductor (CMOS)-/low voltage transistor-transistor logic (LVTTL)-compatible parallel interface. All switches are independently controllable.Multifunction pin names may be referenced by their relevant function only. ADGM1001/ADGM1002/ADGM1003 Key Specifications Model Bandwidth Maximum RF Power (dBm) DC Signal Range (V) Maximum DC Current (mA) ADGM1001 DC to 34 GHz 33 ?6 200 ADGM1002 DC to 20 GHz 30 ?5 150 ADGM1003? DC to 16 GHz 27 ?3 75 APPLICATIONS ATE load and probe boards DC and high speed loop back testing Relay replacements Reconfigurable filters and attenuators Military and microwave radios Cellular infrastructure: 5G mmWave Supports digital standards: PCIe Gen4/Gen5/Gen6, USB 3 and USB 4, and PAM 4

The Analog Devices, Inc., amplifier mezzanine card (AMC) analog-to-digital converter (ADC) driver evaluates the performance of amplifiers in 8-lead, single and dual SOIC, 6-lead single SOT23, 8-lead dual MSOP, and 16-lead LFCSP packages. This add on board can be inserted on ADC evaluation boards using its 7-pin header. Figure 1 shows the AMC mounted on an Analog Devices, Inc., ADC evaluation board. The AMC can support any of Analog Devices operational amplifiers and ADC drivers in different packages. The user can configure the ADC driver as a Sallen-Key low-pass, high-pass, or band-pass filter, as a multiple feedback low-pass, high-pass, or band-pass filter, or as an inverting and noninverting operational amplifier. The user can also configure the AMC to drive a single-ended, fully differential, or a single-ended signal to a differential ADC. Optimized power and ground planes ensure low noise and high speed operation. Component placement and power supply bypassing are optimized for maximum circuit flexibility and performance. The AMC evaluation board accepts 0402 or 0603 surface mount technology (SMT) components, 1206 bypass capacitors, and 2.54 mm headers. All components are placed on the primary side. No components are placed on the secondary side.

Demonstration circuit EVAL-LT8692S-AZ is an ultracompact 4 rail power supply featuring the LT8692S, a 42V quad monolithic synchronous step-down Silent Switcher®. The demo circuit is designed for 5V, 3.3V, 1.8V, and 1.2V outputs from a nominal 12V input. The 3.3V, 1.8V and 1.2V converters are powered from the high voltage buck regulator with 5V output, which is powered from a wide range of 6.2V to 42V input. The current capability is 2A for the channel 1, and 1A for the low voltage channels. Internal soft-start, individual current limit, independent enable for each channel simplify the complex design of quad-output power converters. All regulators can be synchronized to a common external clock input or internal oscillator of 2MHz. The table in the demo manual summarizes the performance of the demo board at room temperature. The circuit can be easily modified for different applications. The LT8692S data sheet gives a complete description of the part, operation and application information. The data sheet must be read in conjunction with the quick start guide for demo circuit EVAL-LT8692S-AZ.

The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The AD9249 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO?1, DCO?2) for capturing data on the output and frame clock outputs (FCO?1, FCO?2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation.The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9249 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Small Footprint. Sixteen ADCs are contained in a small, 10 mm ? 10 mm package. Low Power of 35 mW/Channel at 20 MSPS with scalable power options. Ease of Use. Data clock outputs (DCO?1, DCO?2) operate at frequencies of up to 455 MHz and support double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.APPLICATIONS Medical imaging Communications receivers Multichannel data acquisition