Demonstration circuit 2523A is an 18V, 8.5A (continuous)/12A (peak) synchronous step-down Silent Switcher® with 16µA quiescent current featuring the LT8652S. The LT8652S is a compact, high efficiency, high speed synchronous monolithic step-down switching with the second generation Silent Switcher structure that minimizes EMI and reduces PCB layout sensitivity. Top and bottom power switches, compensation components and other necessary circuits are inside of the LT8652S to minimize external components and simplify design. The demo board has two outputs: 3.3V and 1.2V from a 3.6V to 18V input. The wide input range allows a variety of input sources, such as automotive batteries and industrial supplies. The SYNC pin on the demo board is grounded by default for low ripple Burst Mode® operation. Move JP2 to FCM without SSM position can change the operation mode to forced continuous mode operation. Once JP2 is on FCM with SSM position, VCC is applied to the SYNC pin for low EMI spread spectrum operation. To synchronous to an external clock, move JP2 to SYNC and apply the external clock to the SYNC turret. The demonstration circuit 2523A runs at 2MHz to minimize solution size. The peak efficiency is 90%. The IC temperature rise is less than 70°C when both channels run at full load, 8.5A each, at 2MHz. The demo board has EMI filters installed for both channels. To use the EMI filter, the input should be tied to VEMI1/VEMI2, not VIN1/VIN2. The LT8652S data sheet gives a complete description of the part, operation and application information. The data sheet must be read in conjunction with this demo manual for DC2523A.

DC690A: Demo Board for the LT3420 Photoflash Capacitor Chargers with Automatic Refresh.

Demonstration circuit SCP-LT8330-EVALZ features the LT8330, a boost/SEPIC/inverting converter with a 1A, 60V switch. The demo circuit is specifically a boost converter with an operating input voltage range from 10V to 36V and an output voltage of 48V. With a 12V input, the maximum output current is 135mA. Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely: SCP-INPUT-EVALZ SCP-OUTPUT-EVALZ SCP-FILTER-EVALZ SCP-THRUBRD-EVALZ SCP-1X2BKOUT-EVALZ SCP-1X5BKOUT-EVALZ SCP-5X1-EVALZ   To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design. Note that the Demo Manual does not cover details important to the operation and configuration regarding the LT8330. Please refer to the LT8330 datasheet for a complete description of the part.

The ADAR4002 is a very low power broadband bi-directional single channel true time delay unit (TDU) and a digital step attenuator (DSA). The IC has 18.5 GHz of bandwidth over a frequency range of 0.5 GHz to 19 GHz with 50 ? input impedance at both RF ports. The TDU has two programmable maximum time delays, each with 7-bit control: Range 0 has a maximum delay of 508ps with a resolution of 4ps. This range is used at lower frequencies and where the ADAR4002 has less loss. Range 1 has a maximum delay of 254ps and a resolution of 2ps. This range has less loss compared to Range 0 and is useful at higher frequencies. The DSA has 6-bit resolution with an attenuation range of 0 dB to 31.5 dB and a step size of 0.5 dB. The ADAR4002 is designed to provide flexible digital control through either a SPI interface or a shift register to allow daisy chaining multiple chips together. The ADAR4002 contains register memory for 32 TDU+DSA states. The memory combined with on-chip sequencers, allows a fast memory advance via the UPDATE pin.The ADAR4002 is available in a 2 mm ? 3 mm 14-lead LFCSP package and is specified from -40?C to 85?C.APPLICATIONSElectronic steerable antenna arraysMulti-Function ArraysSATCOMRADARData LinksTest Equipment

The AD8370 is a high performance, digitally controlled variable gain amplifier, designed to be used at IF frequencies within communication infrastructure equipment.The part provides two gain control ranges that are controlled through a three wire digital interface, and allow the user to attain fine gain control for maximum receiver sensitivity.The AD8370 has been fully specified for operation at common wireless IF frequencies 70 / 140 / 190 / 240 / 380MHz. The high output compression and fine gain control adjustability makes the AD8370 an ideal choice for to be used within digital receiver AGC circuits for GSM / CDMA2000 / W-CDMA cellular base stations.The AD8370 is fabricated on an advanced silicon bipolar process, operating on a single 3 or 5 volt supply, packaged in space saving 16-lead thin shrunk small outline (TSSOP) package and fully specified over the ?40 to +85 C temperature range. AvailabilitySamples AD8370ARU and an evaluation boards AD8370-EVAL are available.Other Wireless VGA products:AD8367 - 45dB, 500MHz Single Ended, Analog Controlled VGAAD8369 ? 45dB, 600MHz Differential, 3dB Step Digitally Controlled VGA

Demonstration circuit 1471 is a monolithic step-down DC/DC switching regulator featuring the LT3990. The switching frequency is adjustable up to 2.2MHz. The demo circuit is designed for 5V, 350mA output from a 6.5V to 62V input. The wide input range of the LT3990 allows a variety of input sources including automotive batteries and 24V industrial supplies. Low ripple Burst Mode increases the efficiency at the light load while keeping the output ripple below 5mV in a typical application. The part is in shutdown when the EN pin is low and active when the pin is high. The threshold of the EN pin is accurate at 1V when VIN is above 4.2V. Adding a resistor divider from VIN to EN can program the LT3990 to regulate the output only when VIN is above a desired voltage. The catch diode and boost diode are integrated to reduce the components count and solution size. The circuit consumes only 2.5μA of quiescent current.

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.?The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.Product Highlights Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD8122 is a triple, high speed, differential receiver and equalizer that compensates for the transmission losses of UTP and coaxial cables up to 300 meters in length. Various gain stages are summed together to best approximate the inverse frequency response of the cable. Each channel features a high impedance differential input that is ideal for interfacing directly with the cable.The AD8122 has two control inputs for optimal cable compensation, one LPF control input, an input to select between UTP and coax cable, and an output offset adjust input. The cable compensation inputs are used to compensate for different cable lengths; the VPEAK input controls the amount of high frequency peaking and the VGAIN input adjusts the broadband flat gain, which compensates for the flat cable loss. The VFILTER input controls the cutoff frequency of output lowpass filters on each channel. Selection between UTP and coaxial cable compensation responses is determined by the binary COAX/UTP?input, which can be left floating in UTP applications. The VOFFSET pin allows the dc voltage at the output to be adjusted, which can be useful in dc-coupled systems.For added flexibility, the gains of each channel can be set to x1 or x2 using the associated GAIN control pins.The AD8122 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is rated to operate over the extended temperature range of ?40?C to +85?C.APPLICATIONS Keyboard-video-mouse (KVM) Digital signage RGB video over UTP cables Professional video projection and distribution HD video Security video

DC782A-Q: Demo Board for the LTC2249 14-Bit, 80Msps Low Power 3V ADC.

Demonstration circuit 2638A-D is a high efficiency, high density, μModule regulator with 4.5V to 16V input range. The output voltage is adjustable from 0.5V to 3.3V, and it can supply 250A maximum load current. The demo board has five LTM4678 μModule® regulators, and the LTM4678 is a dual 25A or single 50A step-down regulator with PMBus power system management. Please see LTM4678 data sheet for more detailed information. DC2638A-D powers up to default settings and produce power based on configuration resistors without the need for any serial bus communication. This allows easy evaluation of the DC/DC converter. To fully explore the extensive power system management features of the part, download the GUI software LTpowerPlay® onto your PC and use ADI’s I2C/SMBus/PMBus dongle DC1613A to connect to the board. LTpowerPlay allows the user to reconfigure the part on-the-fly and store the configuration in EEPROM, view telemetry of voltage, current, temperature and fault status. GUI Download: The software can be downloaded from: LTpowerPlay. For more details and instructions of LTpowerPlay, please refer to LTpowerPlay GUI for LTM4678 Quick Start Guide.