Demonstration circuit 2419A features the LTC3372 in a multi-output step-down converter. The controller portion of the LTC3372 drives a high output voltage (HV) buck converter which has an input voltage range of 6V to 60V. Its output voltage (VOUT_HV) is nominally 5V but can be configured for either 5V or 3.3V with the VOUTPRG pin. VOUT_HV supplies power to the configurable buck regulator. This regulator provides four low voltage (LV) outputs labelled VOUT1-4. These outputs are 1.2V/2A, 1.8V/2A, 2.5V/2A and 3.3V/2A respectively. When VOUT_HV is configured for 5V, it can supply 6A to the external loads with full load on VOUT1-4. With no load on VOUT1-4, VOUT_HV can supply 10A to the external loads. The LV buck regulator consists of eight power stages that can be arranged in up to four channels. The LV regulator on the DC2419A is setup for four channels of two power stages each. With modifications, the LV buck regulator can be setup for eight different configurations. If VOUT_HV is programmed for 3.3V, then VOUT4 which provides 3.3V/2A will be in dropout. This rail will require an external input voltage to stay in regulation. The LV rails operate at 2MHz and the HV converter operates at one-sixth this frequency or 333kHz. The high frequency of the LV rails allows the use of 4mm × 4mm inductors. The power stage for the HV converter consists of 60V avalanche rated MOSFETs and a 2.2μH 10mm × 10mm inductor. A 4mΩ discrete sense resistor is used to sense current. The low IQ current of the LTC3372 provides high efficiency at light loads. When the VOUT_HV is supplying the nominal 5V, its Burst Mode® efficiency with 1mA load is 90.3% for a 12V input. When the HV converter is off, it only draws 27μA from a 12V input. The LTC3372 data sheet provides a complete description of the IC operation and application information. The data sheet must be read in conjunction with the quick start guide.

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 ? fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC.The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.Product Highlights Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block. Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR). Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.Applications Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless

The ADA4098-1?and ADA4098-2?are single/dual robust, precision, rail-to-rail input and output operational amplifiers (op amps) with inputs that operate from ?VS to +VS and beyond, which is referred to in this data sheet as Over-The-Top?. The devices feature offset voltages of ?VS, independent of the +VS supply.The ADA4098-1 and ADA4098-2 are unity-gain stable and can drive loads requiring up to 20 mA per channel. The devices can also drive capacitive loads as large as 200 pF. The amplifiers are available with low power shutdown.The ADA4098-1 is available in a standard, 6-lead thin small outline transistor (TSOT) package. The ADA4098-2 is available in an 8-lead standard small outline (SOIC_N) package, 8-lead mini small outline package (MSOP), and 10-lead lead-frame chip-scale package (LFCSP).APPLICATIONS Industrial sensor conditioning Supply current sensing Battery and power supply monitoring Front-end amplifiers in abusive environments 4 mA to 20 mA transmitters

The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9255 is suitable for applications in communications, instrumentation, and medical imaging.A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9255 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. ?Pin compatibility with the AD9265, allowing a simple migration up to 16 bits.Applications Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

The ADAR4002 is a very low power broadband bi-directional single channel true time delay unit (TDU) and a digital step attenuator (DSA). The IC has 18.5 GHz of bandwidth over a frequency range of 0.5 GHz to 19 GHz with 50 ? input impedance at both RF ports. The TDU has two programmable maximum time delays, each with 7-bit control: Range 0 has a maximum delay of 508ps with a resolution of 4ps. This range is used at lower frequencies and where the ADAR4002 has less loss. Range 1 has a maximum delay of 254ps and a resolution of 2ps. This range has less loss compared to Range 0 and is useful at higher frequencies. The DSA has 6-bit resolution with an attenuation range of 0 dB to 31.5 dB and a step size of 0.5 dB. The ADAR4002 is designed to provide flexible digital control through either a SPI interface or a shift register to allow daisy chaining multiple chips together. The ADAR4002 contains register memory for 32 TDU+DSA states. The memory combined with on-chip sequencers, allows a fast memory advance via the UPDATE pin.The ADAR4002 is available in a 2 mm ? 3 mm 14-lead LFCSP package and is specified from -40?C to 85?C.APPLICATIONSElectronic steerable antenna arraysMulti-Function ArraysSATCOMRADARData LinksTest Equipment

Demonstration circuit 1989B-B is a high efficiency, high density, μModule regulator with 4.5V to 17V input range. The output voltage is adjustable from 0.5V to 4V, and it can supply 75A maximum load current. The demo board has three LTM4676A μModule regulators, and the LTM4676A is a dual 13A or single 26A step-down regulator with PMBus power system management. Please see LTM4676A data sheet for more detailed information.

The HMC415LP3(E) is a high efficiency GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC Power amplifier which operates between 4.9 and 5.9 GHz. The amplifier is packaged in a low cost, leadless surface mount package with an exposed base for improved RF and thermal performance. With a minimum of external components, the amplifier provides 20 dB of gain, +26 dBm of saturated power, and 34% PAE from a +3V supply voltage. Vpd can be used for full power down or RF output power/current control. For +15 dBm OFDM output power (64 QAM, 54 Mbps), the HMC415LP3(E) achieves an error vector magnitude (EVM) of 3.7% meeting 802.11a linearity requirements.Applications 802.11a WLAN HiperLAN WLAN Access Points UNII & ISM Radios

DC792A: Demo Board for the LT5525 High Linearity, Low Power Downconverting Mixer.

The LTC5532 is an RF power detector for RF applications operating in the 300MHz to 7GHz range. A temperature compensated Schottky diode peak detector and buffer amplifier are combined in a small ThinSOT? or (2mm x 2mm) DFN package. The supply voltage range is optimized for operation from a single lithium-ion cell or 3x NiMH.The RF input voltage is peak detected using an on-chip Schottky diode. The detected voltage is buffered and supplied to the VOUT pin.The LTC5532 output buffer gain is set via external resistors. The initial starting voltage of 120mV ?35mV can be precisely adjusted using the VOS pin.The LTC5532 operates with RF input power levels from ?32dBm to 10dBmApplications 802.11a, 802.11b, 802.11g, 802.15 Multimode Mobile Phone Products Optical Data Links Wireless Data Modems Wireless and Cable Infrastructure RF Power Alarm Envelope Detector

The AD91661 is a high performance, wideband, on-chip vector signal generator composed of a high speed JESD204B serializer/deserializer (SERDES) interface, a flexible 16-bit digital datapath, a inphase/quadrature (I/Q) digital-to-analog converter (DAC) core, and an integrated differential to single-ended outputbuffer amplifier, matched to a 50 ? load up to 10 GHz.The DAC core is based on a quad-switch architecture, which is configurable to increase the effective DAC core update rate of up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a direct digital synthesizer (DDS) block with multiple numerically controlled oscillators (NCOs) supporting fast frequency hopping (FFH), and additional FIR85 and inverse sinc filter stages to allow flexible spectrum planning.The differential to single-ended buffer eliminates the need for a wideband balun, and supports the full analog output bandwidth of the DAC core. DC coupling the output allows baseband waveform generation without the need for external bias tees or similar circuitry, which makes the AD9166 uniquely suited for the mostdemanding high speed ultrawideband RF transmit applications. The various filter stages enable the AD9166 to be configured for lower data rates, while maintaining higher DAC clock rates to ease the filtering requirements and reduce the overall system size, weight, and power.The data interface receiver consists of up to eight JESD204B SERDES lanes, each capable of carrying up to 12.5 Gbps. To enable maximum flexibility, the receiver is fully configurable according to the data rate, number of SERDES lanes, and lane mapping required by the JESD204B transmitter.In 2? nonreturn-to-zero (NRZ) mode of operation (with FIR85 enabled), the AD9166 can reconstruct RF carriers from true dc to the edge of the third Nyquist zone, or an analog bandwidth of true dc up to 9 GHz.In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power and maintaining a performance comparable to 2? NRZ mode.In baseband modes, such as return-to-zero (RZ) and 1? NRZ, the AD9166 is ideal to reconstruct RF carriers from true dc to the edge of the first Nyquist zone while consuming lower power compared to 2? NRZ mode.The quadrature DDS block can be configured as a digital upconverter to upconvert I/Q data samples to the desired location across the spectrum, in all three Nyquist zones.The DDS also consists of a bank of 32 numerically controlled oscillators (NCOs), each with its own 32-bit phase accumulator. When combined with a 100 MHz serial peripheral interface (SPI), the DDS allows a phase coherent FFH, with a phase settling time as low as 300 ns.The AD9166 is configured using a common SPI interface that monitors the status of all registers. The AD9166 is offered in a 324-ball, 15 mm ? 15 mm, 0.8 mm pitch BGA_ED package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 9 GHz. Fully supports zero IF and other dc-coupled applications. Up to an eight-lane JESD204B SERDES interface, with various features to allow flexibility when interfacing to a JESD204B transmitter.Applications Instrumentation: automated test equipment, electronic test and measurement, arbitrary waveform generators Electronic warfare: radars, jammers Broadband communications systems Local oscillator drivers1 Protected by U.S. Patents 6,842,132 and 7,796,971.