Demonstration circuit SCP-ADP150-EVALZ features the ADP150, an ultralow noise (9μV), low dropout, linear regulator that operates from 2.2V to 5.5V and provides up to 150mA of output current. ADP150AUJZ-3.3-R7 fixed volt-age IC is installed on this board. Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely: SCP-INPUT-EVALZ SCP-OUTPUT-EVALZ SCP-FILTER-EVALZ SCP-THRUBRD-EVALZ SCP-1X2BKOUT-EVALZ SCP-1X5BKOUT-EVALZ SCP-5X1-EVALZ   To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design. Note that the Demo Manual does not cover details important to the operation and configuration regarding the ADP150. Please refer to the ADP150 datasheet for a complete description of the part.

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM)from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 isavailable in a 56-lead LFCSP. The AD9152 is a member of theTxDAC+? family.Product Highlights Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with an 8 mm ? 8 mm footprint. ?Applications Wireless communications Multicarrier LTE and GSM base stations Wideband repeaters Software defined radios Wideband communications Point to point microwave radios LMDS/MMDS Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment

The ADP5585 is a 10I/O port expander with built-in keypad matrix decoder, programmable logic, reset generator, and PWM generator. I/O expander ICs are used in portable devices (phones, remote controls, & cameras) and non-portable applications (healthcare, industrial & instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs.The ADP5585 handles all key scanning and decoding and can flag the main processor via an interrupt line that new key events have occurred. GPI changes and logic changes can also be tracked as events via the FIFO, eliminating the need to monitor different registers for event changes. The ADP5585 is equipped with a FIFO to store up to 16 events. Events can be read back by the processor via an I2C compatible interface.The ADP5585 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions.The programmable logic functions allow common logic requirements to be integrated as part of the GPIO expander, saving board area and cost.APPLICATIONS Keypad entries and input/output expansion capabilities Smart phones, remote controls, and cameras Healthcare, industrial, and instrumentation

The LTC5584 is a direct conversion quadrature demodulator optimized for high linearity receiver applications in the 30MHz to 1.4GHz frequency range. It is also usable in the 10MHz to 30MHz and 1.4GHz to 2GHz ranges with reduced performance. It is suitable for communications receivers where an RF signal is directly converted into I and Q baseband signals with bandwidth of 530MHz or higher. The LTC5584 incorporates balanced I and Q mixers, LO buffer amplifiers and a precision, high frequency quadrature phase shifter. In addition, the LTC5584 provides four analog control voltage interface pins for IIP2 and DC offset correction, greatly simplifying system calibration.The high linearity of the LTC5584 provides excellent spurfree dynamic range for the receiver. This direct conversion demodulator can eliminate the need for intermediate frequency (IF) signal processing, as well as the corresponding requirements for image filtering and IF filtering. These I/Q outputs can interface directly to channel-select filters (LPFs) or to baseband amplifiers.Applications LTE/W-CDMA/TD-SCDMA Base Station Receivers Wideband DPD Receivers Point-To-Point Broadband Radios High Linearity Direct Conversion I/Q Receivers Image Rejection Receivers

The HMC1065LP4E is a compact GaAs MMIC Image Reject Low Noise Converter in a leadless RoHS compliant SMT package. This device provides a small signal conversion gain of 13 dB with 17 dBc of image rejection, and -2 dBm Input IP3. The HMC1065LP4E utilizes an RF LNA followed by an I/Q mixer which is driven by an active X2 multiplier. IF1 and IF2 mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of the unwanted sideband. The HMC1065LP4E is a much smaller alternative to hybrid style image reject downconverter assemblies and it eliminates the need for wire bonding by allowing the use of surface mount manufacturing techniques.APPLICATIONS Point-to-Point & Point-to-Multi-Point Radio Satellite Communications Sensors

The LT5506 is a 40MHz to 500MHz monolithic integrated quadrature demodulator with variable gain amplifier (VGA), designed for low voltage operation. It supports standards that use a linear modulation format. The chip consists of a VGA, quadrature down-converting mixers and lowpass noise filters. The LO port consists of a divide-by-two stage and LO buffers. The IC provides all building blocks for IF down-conversion to I and Q baseband signals with a single supply voltage of 1.8V to 5.25V. The VGA gain has a linear-in- dB relationship to the control input voltage. Hard-clipping amplifiers at the mixer outputs reduce the recovery time from a signal overload condition. The lowpass filters reduce the out-of-band noise and spurious frequency components. The cut-off frequency of the noise filters is approximately 8.8MHz. The external 2xLO frequency is required to be twice the IF input frequency for the mixers. The standby mode provides reduced supply current and fast transient response into the normal operating mode when the I/Q outputs are AC-coupled to a baseband chip.Applications IEEE802.11 High Speed Wireless LAN Wireless Local Loop

The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit,20/40/65/80 MSPS analog-to-digital converter (ADC). It featuresa high performance sample-and-hold circuit and on-chip voltagereference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 10-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximize flexibilityand minimize system cost, such as programmable clock and dataalignment and programmable digital test pattern generation. Theavailable digital test patterns include built-in deterministic andpseudorandom patterns, along with custom user-defined testpatterns entered via the serial port interface (SPI).A differential clock input with selectable internal 1 to 8 divide ratiocontrols all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, ortwos complement format. A data output clock (DCO) is providedto ensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9609 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (?40?Cto +85?C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingPRODUCT HIGHLIGHTS1. The AD9609 operates from a single 1.8 V analog powersupply and features a separate digital output driver supplyto accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performancefor input frequencies up to 200 MHz and is designed for lowcost, low power, and ease of use.3. A standard serial port interface supports various productfeatures and functions, such as data output formatting,internal clock divider, power-down, DCO and data output(D9 to D0) timing and offset adjustments, and voltagereference modes.4. The AD9609 is packaged in a 32-lead RoHS compliantLFCSP that is pin compatible with the AD9629 12-bit ADCand the AD9649 14-bit ADC, enabling a simple migrationpath between 10-bit and 14-bit converters sampling from20 MSPS to 80 MSPS.

Demonstration circuits 1645A-A, 1645A-B, 1645A-C and 1645A-D feature the LTM8061, a 32V, 2A μModule® Li-Ion battery charger. Operating from a 6.5V to 32V input source, the 1645A-A and 1645A-B demo circuits charge single cell Li-Ion batteries to float voltages of 4.1V or 4.2V respectively. The 1645A-C and 1645A-D demo circuits operate from a 12V to 32V input source, and charge dual cell Li-Ion battery packs to float voltages of 8.2V or 8.4V. JP1 turns the converter on or off. JP2 allows for easy selection of C/10 or timer charge termination.

The LTC4126-ADJ is a low-power wireless single-cell Li-Ion battery charger with an integrated step-down DC/DC regulator. The step-down regulator is a low-noise multimode charge pump which is powered from the battery and provides a regulated 1.2V at the output. The switching frequency is set to either 50kHz or 75kHz depending on the mode to keep any switching noise out of the audible range.The constant-current constant-voltage Li-Ion battery charger has automatic recharge, automatic termination by safety timer, and battery temperature monitoring via an NTC pin. Charge current is programmable from 1mA to 50mA via an external resistor. Undervoltage protection disconnects the battery from all loads when the battery voltage is below 3.0V.The small package and minimal external component count make the LTC4126-ADJ and its variants suitable for hearing aid applications and other low power portable devices. See the chart in the data sheet.APPLICATIONSHearing AidsLow Power Li-Ion Powered DevicesWireless HeadsetsIoT Wearables

Demonstration circuit 2350B features the LTC6813-1, 18-channel battery-stack monitor. Multiple boards can be linked through a 2-wire isolated serial interface (isoSPI™) to monitor a long series of cells in a stack. The DC2350B demo board also features reversible isoSPI enabling a redundant communication path. The PCB, components, and DuraClik connectors are optimized for low EMI susceptibility and emissions. The DC2350B can communicate to a PC by connecting a DC2792B dual master isoSPI together with DC2026C Linduino® One. The DC2026 must be loaded with the appropriate program (called a sketch) to control the battery-stack monitor IC and receive data through a USB serial port. The DC2026 provides a standard SPI interface which can be translated to isoSPI and then connected to a DC2350B isoSPI port (J4 or J5 connector). The DC2792B companion board provides two SPI-isoSPI channels for reversible operation.