The HMC760LC4B is a SiGe monolithic, fully differential, single rank, track-and-hold (T/H) that provides unprecedented bandwidth and dynamic-range performance to wideband sampled signal systems. The T/H offers precision signal sampling over 5 GHz bandwidth, with 9 to 10-bit linearity from DC to 5 GHz input frequency, 0.9 mV noise, and <70 fs random aperture jitter. The device can be clocked to 4 GS/s with minimal dynamic range loss. The T/H can be used to expand the bandwidth and/or high-frequency linearity of high-speed A/D conversion and signal acquisition systems.APPLICATIONS RF ATE Applications Digital Sampling Oscilloscopes RF Demodulation Systems Digital Receiver Systems High Speed Peak Detectors Software Defined Radio Radar, ECM & ELINT Systems High Speed DAC De-Glitching

The LTC3890-3 is a high performance dual step-down switching regulator DC/DC controller that drives all N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows a phase-lockable frequency of up to 850kHz. Power loss and supply noise are minimized by operating the two controller output stages out-of-phase.The 50?A no-load quiescent current extends operating life in battery-powered systems. OPTI-LOOP? compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. A wide 4V to 60V input supply range encompasses a wide range of intermediate bus voltages and battery chemistries.Independent TRACK/SS pins for each controller ramp the output voltages during start-up. Current mode control limits the inductor current during short-circuit conditions. The PLLIN/MODE pin selects among Burst Mode operation, pulse-skipping mode, or continuous conduction mode at light loads.For versions with different and/or additional features, see the LTC3890 family summary, Table 1, in the Pin Functions section of this data sheet. LTC3890 LTC3890-1 LTC3890-2 LTC3890-3 Adjustable Current Limit Yes No Yes No CLKOUT/PHASMD for Multiphase Operation Yes No Yes No Number of PGood Outputs 2 1 2 1 OVP ? Bottom Gate Crowbar Yes Yes No No Current Limit Foldback Yes Yes No No Light Load Operation when Synced to External Clock Forced Continuous Forced Continuous Pulse Skipping Pulse Skipping SENSE Pins Common Mode Range Common Mode < 0.5V Requires VFB < 0.65V Common Mode < 0.5V Requires VFB < 0.65V Not Dependant on VFB. Easy to make a non-synchronous Boost or SEPIC Not Dependant on VFB. Easy to make a non-synchronous Boost or SEPIC Package 5X5 QFN-32 SSOP-28 5X5 QFN-32 SSOP-28 Applications Automotive Always-On Systems Battery Operated Digital Devices Distributed DC Power Systems

The HMC7357 is a three-stage GaAs pHEMT MMIC Medium Power Amplifier that operates between 5.5 and 8.5 GHz. The amplifier provides 29 dB of gain and +35 dBm of saturated output power at 34% PAE from a +8V supply. With an excellent Output IP3 of +41.5 dBm, the HMC7357 is ideal for linear applications such as high capacity point-to-point and point-to-multi-point radios or VSAT/SATCOM applications demanding +35 dBm of efficient saturated output power. The RF I/Os are internally matched to 50 Ohms for ease of use. The HMC7357 is packaged in a leadless 5x5 mm plastic surface mount package and is compatible with surface mount manufacturing techniques.Applications Point-to-Point Radios Point-to-Multi-Point Radios VSAT & SATCOM

The LTC3722-1/LTC3722-2 phase-shift PWM controllers provide all of the control and protection functions necessary to implement a high efficiency, zero voltage switched (ZVS), full bridge power converter. Adaptive ZVS circuitry delays the turn-on signals for each MOSFET independent of internal and external component tolerances. Manual delay set mode enables secondary side control operation or direct control of switch turn-on delays. The LTC3722-1/LTC3722-2 feature adjustable synchronous rectifier timing for optimal efficiency. A UVLO program input provides accurate system turn-on and turn-off voltages. The LTC3722-1 features peak current mode control with programmable slope compensation and leading edge blanking, while the LTC3722-2 employs voltage mode control. The LTC3722-1/LTC3722-2 feature extremely low operating and start-up currents. Both devices include a full range of protection features and are available in the 24-pin surface mount GN package.Applications Telecommunications, Infrastructure Power Systems Distributed Power Architectures Server Power Supplies

The AD8333 is a dual-phase shifter and I/Q demodulator that enables coherent summing and phase alignment of multiple analog data channels. It is the first solid-state device suitable forbeamformer circuits, such as those used in high performance medical ultrasound equipment featuring CW Doppler. The RF inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the?AD8332.A divide-by-4 circuit generates the internal 0? and 90? phases of the local oscillator (LO) that drive the mixers of a pair of matched I/Q demodulators.The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment.The AD8333 features an asynchronous reset pin. When used in arrays, the reset pin sets all the LO dividers in the same state. Sixteen discrete phase rotations in 22.5? increments can be selected independently for each channel. For example, if Channel 1 is used as a reference and the RF signal applied to Channel 2 has an I/Q phase lead of 45?, Channel 2 can be phase aligned with Channel 1 by choosing the correct code.Phase shift is defined by the output of one channel relative to another. For example, if the code of Channel 1 is adjusted to 0000 and that of Channel 2 to 0001 and the same signal is applied to both RF inputs, the output of Channel 2 leads that of Channel 1 by 22.5?.The I and Q outputs are provided as currents to facilitate summation. The summed current outputs are converted to voltages by a high dynamic-range, current-to-voltage (I-V) converter, such as the AD8021, configured as a transimpedance amplifier. The resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS).The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance amplifier is needed for each of the I and Q outputs, four in total for the dual I/Q demodulator.The dynamic range is 159 dB/Hz at each I and Q output, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design.The AD8333 is available in a 32-lead LFCSP (5 mm ? 5 mm) package for the industrial temperature range of ?40?C to +85?C.Applications Medical imaging (CW ultrasound beamforming) Phased array systems (radar and adaptive antennas) Communication receivers

The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time ?-? (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use. The 16 ADC cores features a first-order, CTSD modulator architecture with integrated, background nonlinearity correction logic and self cancelling dither. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. Each ADC has a signal processing tile to filter out of band shaped noise from the ?-? ADC and reduce the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a quadrature digital downconverter (DDC) with multiple finite input response (FIR) decimation filters (decimate by J block), or up to three quadrature DDC channels with averaging decimation filters for data gating applications. Users can configure the Subclass 1 JESD204B based, high speed serialized output in a variety of lane configurations (up to four), depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, TRIG?, and SYNCINB? input pins. The AD9083 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI). The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is specified over the ?40?C to +85?C industrial temperature range.This product is protected by a US patent.APPLICATIONS Millimeter wave imaging Electronic beam forming and phased arrays Multichannel wideband receivers Electronic support measuresPRODUCT HIGHLIGHTS Continuous time, ?-? analog-to-digital converters (ADCs) support signal bandwidths of up to 125 MHz with low power and minimal filtering. Integrated digital processing blocks reduce data payload and lower overall system cost. Configurable JESD204B interface reduces printed circuit board (PCB) complexity. Flexible power-down options. SPI interface controls various product features and functions to meet specific system requirements. Small, 9 mm ? 9 mm, 100-ball CSP_BGA package, simple interface, and integrated digital processing save PCB space.

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

The HMC1061LC5 is a silicon germanium (SiGe), monolithic, fully differential, dual rank, track-and-hold amplifier that provides unprecedented bandwidth and dynamic range performance to wideband sampled signal systems. The track-and-hold amplifier offers precision signal sampling over an 18 GHz bandwidth, with 9-bit to 10-bit linearity from dc to beyond 5 GHz input frequency, 1.45 mV noise, and <70 fs random aperture jitter.The HMC1061LC5 can be clocked to 4 GSPS with minimal dynamic range loss. The track-and-hold amplifier can be used to expand the bandwidth and/or high frequency linearity of high speed analog to digital conversion and signal acquisition systems. Wideband data acquisition systems with multi GHz required bandwidth for a variety of applications, such as software defined radio, radar systems, electronic warfare (EW), electronic intelligence (ELINT), and automated test equipment (ATE).Applications RF ATE applications Digital sampling oscilloscopes RF demodulation systems Digital receiver systems High speed peak detectors Software defined radio Radar, electronic counter measures (ECM), and electronic intelligence systems High speed digital-to-analog converter (DAC) deglitching

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.Applications Communications Diversity multi-band, multi-mode digital receivers 3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Radar Digital oscilloscopes High speed data acquisition systems DOCSIS CMTS upstream receive paths HFC digital reverse path receivers

Demonstration circuit 2785A-A features the LTM4668 µModule® regulator, a Quad 1.2A high efficiency step-down regulator. DC2785A-A has an operating input voltage range of 2.7V to 17V and can provide an output current of up to 1.5A. The output voltage can be programmed from 0.6V up to 1.8V. The LTM4668 is a complete DC/DC point of load regulator in a thermally enhanced 6.25mm × 6.25mm × 2.1mm BGA package requiring only a few input and output capacitors. External clock synchronization is available through the CLKIN turret. The LTM4668 data sheet must be read in conjunction with this demo manual for working on or modifying demo circuit 2785A-A.