The AD8332 is a dual channel ultralow noise, linear-in-dB, variable gain amplifier (VGA). Optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 MHz.Included in each channel are an ultralow noise preamplifier (LNA), an X-AMP? VGA with 48 dB of gain range, and a selectable gain postamplifier with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs. Using a single resistor, the LNA input impedance can be adjusted to match a signal source without compromising noise performance.The 48 dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Differential signal paths result in superb second- and third-order distortion performance and low crosstalk.The operating temperature range is -40?C to +85?C. The AD8332 is available in a 28-lead TSSOP and 32-lead LFCSP packages.The AD8332 is a dual version of the single AD8331 and quad AD8334.Applications Ultrasound and sonar time-gain controls High performance automatic gain control (AGC) systems I/Q signal processing High speed, dual ADC drivers

DC231A: Demo Board for the LT1610 1.7MHz, Single Cell Micropower DC/DC Converter.

The ADM2482E/ADM2487E are isolated data transceivers with ?15 kV ESD protection and are suitable for high speed, half-duplex or full-duplex communication on multipoint transmission lines. For half-duplex operation, the transmitter outputs and receiver inputs share the same transmission line. Transmitter Output Pin Y is linked externally to Receiver Input Pin A, and Transmitter Output Pin Z to Receiver Input Pin B. The parts are designed for balanced transmission lines and comply with TIA/EIA- 485-A-98 and ISO 8482:1987(E).The devices employ the Analog Devices, Inc., iCoupler? technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. An on-chip oscillator outputs a pair of square waveforms that drive an external transformer to provide isolated power. The logic side of the device can be powered with either a 5 V or a 3.3 V supply, and the bus side is powered with an isolated 3.3 V supply.The ADM2482E/ADM2487E driver has an active high enable, and the receiver has an active low enable. The driver output enters a high impedance state when the driver enable signal is low. The receiver output enters a high impedance state when the receiver enable signal is high.The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range of ?40?C to +85?C and is available in a 16-lead, wide-body SOIC package.Applications Isolated RS-485/RS-422 interfaces Industrial field networks Multipoint data transmission systems

DC1593A-B: Demo Board for the LTC2635-12 Quad 12-Bit I2C VOUT DACs with 10ppm/°C Reference.

The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V to5.5 V, IEC electrostatic discharge (ESD) protected RS-485transceivers, allowing the devices to withstand ?12 kV contactdischarges on the transceiver bus pins without latch-up ordamage. The ADM3062E/ADM3064E/ADM3066E/ADM3068Efeature a VIO logic supply pin that allows a flexible digital interfacecapable of operating as low as 1.62 V. The ADM3065E/ADM3066E/ADM3067E/ADM3068E aresuitable for high speed, 50 Mbps, bidirectional data communication on multipoint bus transmission lines. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E feature a 1/4 unit load inputimpedance that allows up to 128 transceivers on a bus. TheADM3061E/ADM3062E/ADM3063E/ADM3064E models offerall of the same features as the ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a low 500 kbps data rate thatis suitable for operation over long cable runs. The ADM3061E/ADM3062E/ADM3065E/ADM3066E are halfduplex RS-485 transceivers, fully compliant to the PROFIBUS?standard with increased 2.1 V bus differential voltage at VCC ?4.5 V. The ADM3063E/ADM3064E/ADM3067E/ADM3068Eare full duplex RS-485 transceiver options. The RS-485 transceivers are available in a number of spacesaving packages, including the 10-lead, 3 mm ? 3 mm lead framechip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm ? 3 mmmini small outline package (MSOP), and the 8-lead or 14-lead,narrow body standard small outline packages (SOIC_N).Models with operating temperature ranges of ?40?C to +125?Cand ?40?C to +85?C are available. Excessive power dissipation caused by bus contention or byoutput shorting is prevented by a thermal shutdown circuit. If asignificant temperature increase is detected in the internal drivercircuitry during fault conditions, this feature forces the driveroutput into a high impedance state. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E guarantee alogic high receiver output when the receiver inputs are shorted,open, or connected to a terminated transmission line with alldrivers disabled. Table 2 in the data sheet presents an overview of the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E data rate capability across temperature, power supply,and package options. Refer to the Ordering Guide section formodel numbering.APPLICATIONS Industrial fieldbuses Process control Building automation PROFIBUS networks Motor control servo drives and encoders?

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

DC1012A-B: Demo Board for the LTC2497 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface

The ADP2138 and ADP2139 are high efficiency, low quiescent current, synchronous step-down dc-to-dc converters. The ADP2139 has the additional feature of an internal discharge switch. The total solution requires only three tiny external components. When the MODE pin is set high, the buck regulator operates in forced PWM mode, which provides low peak-to-peak ripple for power supply noise sensitive loads at the expense of light load efficiency. When the MODE pin is set low, the buck regulator automatically switches operating modes, depending on the load current level. At higher output loads, the buck regulator operates in PWM mode. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving light load efficiency.The ADP2138/ADP2139 operate on input voltages of 2.3 V to 5.5 V, which allows for single lithium or lithium polymer cell, multiple alkaline or NiMH cell, PCMCIA, USB, and other standard power sources. The maximum load current of 800 mA is achievable across the input voltage range.The ADP2138/ADP2139 are available in fixed output voltages of 3.3 V, 3.0 V, 2.8 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and 0.8 V. All versions include an internal power switch and synchronous rectifier for minimal external part count and high efficiency. The ADP2138/ADP2139 have internal soft start and they are internally compensated. During logic controlled shutdown, the input is disconnected from the output and the ADP2138/ADP2139 draw 0.2 ?A (typical) from the input source.Other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup. The ADP2138/ADP2139 are available in a 6-ball wafer level chip scale package (WLCSP).Applications PDAs and palmtop computers Wireless handsets Digital audio, portable media players Digital cameras, GPS navigation units

DC1094A: Demo Board for LTC4095 Standalone USB Li-Ion/Polymer Battery Charger in 2mm x 2mm DFN

The ADL5501 is a mean-responding power detector for use in high frequency receiver and transmitter signal chains from 50 MHz to 6 GHz. It is easy to apply, requiring only a single supply between 2.7 V and 5.5 V and a power supply decoupling capacitor. The input is internally ac-coupled and has a nominal input impedance of 50 ?. The output is a linear-responding dc voltage with a conversion gain of 6.3 V/V rms at 900 MHz.The ADL5501 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as CDMA-, CDMA2000-, W-CDMA-, and QPSK-/QAM-based OFDM waveforms. The on-chip modulation filter provides adequate averaging for most waveforms.The on-chip, 100 ? series resistance at the output, combined with an external shunt capacitor, creates a low-pass filter response that reduces the residual ripple in the dc output voltage. For more complex waveforms, an external capacitor at the FLTR pin can be used for supplementary signal demodulation.The ADL5501 offers excellent temperature stability across a 30 dB range and near 0 dB measurement error across temperature over the top portion of the dynamic range. In addition to its temperature stability, the ADL5501 offers low process variations that further reduce calibration complexity.The ADL5501 operates from ?40?C to +85?C and is available in a small 6-lead SC-70 package. It is fabricated on a proprietary high fT silicon bipolar process.ApplicationsMeasurement of CDMA-, CDMA2000-, W-CDMA-, and QPSK-/ QAM-based OFDM, and other complex modulationwaveforms RF transmitter or receiver power measurement