Demonstration circuit 1626A is a dual output 1.5V/15A and 1.2V/15A synchronous buck converter operating with a switching frequency of 300kHz over an input voltage range of 4.5V to 26V. The demo board comes in two versions. The -A version uses inductor DCR current sensing with an iron powder inductor for high efficiency. The -B version uses a 2.5mΩ sense resistor for accurate current sensing with a low DCR ferrite inductor.

Together with an external loop filter and a voltage controlled crystal oscillator (VCXO), the HMC1031 forms a complete clock generator solution targeted at low frequency jitter attenuation and reference clock generation applications.The HMC1031 features a low power integer N divider, support-ing divide ratios of 1, 5, and 10, which is controlled via external hardware pins and requires no serial port.The integrated phase detector and charge pump are capable of operating at up to 140 MHz, and a maximum VCXO input of 500 MHz ensures frequency compliance with a wide variety of system clocks and VCXOs.Additional features include an integrated lock detect indicator available on a dedicated hardware pin, and a built in power-down mode.The HMC1031 is housed in an 8-lead MSOP package.APPLICATIONS Low jitter clock generation Low bandwidth (BW) jitter attenuation Low frequency phase-locked loops PLL Frequency translation Oven controlled crystal oscillator (OCXO) frequency multiplier Phase lock clean high frequency references to 10 MHz equipment

The LTC1625 is a synchronous step-down switching regulator controller that drives external N-Channel power MOSFETs using few external components. Current mode control with MOSFET VDS sensing eliminates the need for a sense resistor and improves efficiency. The frequency of a nominal 150kHz internal oscillator can be synchronized to an external clock over a 1.5:1 frequency range.Burst Mode? operation at low load currents reduces switching losses and low dropout operation extends operating time in battery-powered systems. A forced continuous mode control pin can assist secondary winding regulation by disabling Burst Mode operation when the main output is lightly loaded.Fault protection is provided by foldback current limiting and an output overvoltage comparator. An external capacitor attached to the RUN/SS pin provides soft start capability for supply sequencing. A wide supply range allows operation from 3.7V (3.9V for LTC1625I) to 36V at the input and 1.19V to VIN at the output.Applications Notebook and Palmtop Computers, PDAs Cellular Telephones and Wireless Modems Battery Chargers Distributed Power

The LTC4125 is a simple and high performance monolithic full bridge resonant driver capable of delivering over 5W of power wirelessly to a properly tuned receiver. The device controls the current flow in a series connected transmit coil LC network to create a simple, safe and versatile wireless power transmitter.The LTC4125 automatically adjusts its driving frequency to match the LC network resonant frequency. This AutoResonant switching allows the device to deliver maximum power from a low voltage input supply (3V to 5.5V) to a tuned receiver. To optimize system efficiency, the LTC4125 employs a periodic transmit power search and adjusts the transmission power based on the receiver load requirements. The device stops delivering power during a fault condition, or if a foreign object is detected.The LTC4125 also includes a programmable maximum average input current limit and an NTC input as additional means for foreign object and overload protection. The LTC4125 is available in a 20-lead low profile (0.75mm) 4mm ? 5mm QFN package.Applications Hermetically and/or Electrically Insulated Devices Military Sensors and Devices Medical Equipment Industrial Handhelds

DC1299A-B: Demo Board for the LTC6421-20 Dual Matched 1.3GHz Differential Amplifiers/ADC Drivers

DC812A: Demo Board for the LTC2606 16-Bit Rail-to-Rail DACs with I2C Interface.

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The ADAR4002 is a very low power broadband bi-directional single channel true time delay unit (TDU) and a digital step attenuator (DSA). The IC has 18.5 GHz of bandwidth over a frequency range of 0.5 GHz to 19 GHz with 50 ? input impedance at both RF ports. The TDU has two programmable maximum time delays, each with 7-bit control: Range 0 has a maximum delay of 508ps with a resolution of 4ps. This range is used at lower frequencies and where the ADAR4002 has less loss. Range 1 has a maximum delay of 254ps and a resolution of 2ps. This range has less loss compared to Range 0 and is useful at higher frequencies. The DSA has 6-bit resolution with an attenuation range of 0 dB to 31.5 dB and a step size of 0.5 dB. The ADAR4002 is designed to provide flexible digital control through either a SPI interface or a shift register to allow daisy chaining multiple chips together. The ADAR4002 contains register memory for 32 TDU+DSA states. The memory combined with on-chip sequencers, allows a fast memory advance via the UPDATE pin.The ADAR4002 is available in a 2 mm ? 3 mm 14-lead LFCSP package and is specified from -40?C to 85?C.APPLICATIONSElectronic steerable antenna arraysMulti-Function ArraysSATCOMRADARData LinksTest Equipment

The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.The conversion process and data acquisition are controlled using ASYNC and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of ASYNC and conversion is also initiated at this point. There are no pipeline delays associated with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V to VREFA input or a 0 V to 2 ? VREFA with either straight binary or twos complement output coding. The conversion time is determined by the ASCLK frequency because it is also used as the master clock to control the conversion.The DAC section of the AD5590 comprises sixteen 12-bit DACs divided into two groups of eight. Each group has an on-chip reference. The on-board references are off at power-up, allowing the use of external references. The internal references are enabled via a software write.The AD5590 incorporates a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain powered up at this level until a valid write takes place. The DAC contains a power-down feature that reduces the current consumption of the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a user-programmable code: zero scale, midscale, or full scale.The AD5590 contains eight low noise, single-supply amplifiers. These amplifiers can be used for signal conditioning for the ADCs, DACs, or other independent circuitry, if required.APPLICATIONS Optical Line Cards (Monitoring and Control) Base Stations General Purpose Analog I/O Monitoring and control

The LTC3412A is a high efficiency monolithic synchronous, step-down DC/DC converter utilizing a constant frequency, current mode architecture. It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. The internal synchronous power switch with 77m? on-resistance increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. OPTI-LOOP? compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The LTC3412A can be configured for either Burst Mode operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the application requirements.APPLICATIONS Point-of-Load Regulation Notebook Computers Portable Instruments Distributed Power Systems