The ADP5070 is a dual high performance dc-to-dc regulator that generates independently regulated positive and negative rails.The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +39 V and a negative output voltage down to ?39 V below input voltage.The ADP5070 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5070 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI).Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first.The ADP5070 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, both regulators completely disconnect the loads from the input supply to provide a true shutdown.Other key safety features in the ADP5070 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO).The ADP5070 is available in a 20-lead LFCSP or in a 20-lead TSSOP and is rated for a ?40?C to +125?C junction temperature range.Applications Bipolar amplifiers, ADCs, DACs and multiplexers Charge-coupled device (CCD) bias supply Optical module supply RF power amplifier (PA) bias

The AD7655 is a low cost, simultaneous sampling, dual-channel,16-bit, charge redistribution SAR, analog-to-digital converterthat operates from a single 5 V power supply. It contains twolow noise, wide bandwidth, track-and-hold amplifiers that allowsimultaneous sampling, a high speed 16-bit sampling ADC, aninternal conversion clock, error correction circuits, and bothserial and parallel system interface ports. Each track-and-holdhas a multiplexer in front to provide a 4-channel input ADC.The A0 multiplexer control input allows the choice ofsimultaneously sampling input pairs INA1/INB1 (A0 = low) orINA2/INB2 (A0 = high). The part features a very high samplingrate mode (normal) and, for low power applications, a reducedpower mode (impulse) where the power is scaled with thethroughput. Operation is specified from ?40?C to +85?C.Product Highlights Multichannel ADC. The AD7655 features 4-channel inputs with two sample-and-hold circuits that allow simultaneous sampling. Fast Throughput. The AD7655 is a 500 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. Single-Supply Operation. The AD7655 operates from a single 5 V supply. In impulse mode, its power dissipation decreases with throughput. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangements are compatible with both 3 V and 5 V logic.Applications AC motor control 3-phase power control 4-channel data acquisition Uninterrupted power supplies Communications

The AD9517-11?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-1 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-1 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-1 is specified for operation over the industrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1AD9517 is used throughout the data sheet to refer to all the members of the AD9517 family. However, when AD9517-1 is used, it is refers to that specific member of the AD9517 family.

The ADG5243F comprises three independently selectable, singlepole/double-throw (SPDT) switches. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input enables or disables the device. When disabled, all channels are switched off. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. The primary supply voltages define the on-resistance profile, whereas the secondary supply voltages define the voltage level at which the overvoltage protection engages.When no power supplies are present, the channel remains in the off condition, and the switch inputs are high impedance. Undernormal operating conditions, if the analog input signal levels on any Sx pin exceed the positive fault voltage (POSFV) or the negative fault voltage (NEGFV) by a threshold voltage (VT), the channel turns off and that Sx pin becomes high impedance. If the switch is selected to be on, then the drain pin is pulled to the secondary supply voltage that was exceeded. Input signal levels upto ?55 V or +55 V relative to ground are blocked, in both the powered and unpowered conditions.The low capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-andholdapplications, where low glitch switching and fast settling times are required.Note that, throughout this data sheet, multifunction pins, such as IN1/F1, are referred to either by the entire pin name or by asingle function of the pin, for example, IN1, when only that function is relevant.Product Highlights The source pins are protected against voltages greater than?the secondary supply rails, up to ?55 V and +55 V. The source pins are protected against voltages between??55 V and +55 V in an unpowered state. Overvoltage detection with the digital output indicates the?operating state of the switches. Trench isolation guards against latch-up. Optimized for low charge injection and on-capacitance. The ADG5243F can be operated from a dual supply of ?5 V?to ?22 V or a single power supply of 8 V to 44 V.Applications Analog input/output modules? Process control/distributed control systems? Data acquisition? Instrumentation? Avionics? Automatic test equipment? Communication systems? Relay replacement?

Demonstration circuit 1126 is a high density dual output (3.3V/5A and 2.5V/5A) step down converter featuring the LTC3850EUF. The input voltage range is 6.5V to 14V. For applications that have a 5V +/- 0.5V input, the board has an optional resistor to tie the INTVCC pin to the VIN pin. An optional DCR sense circuit allows the converter to use the inductor’s DCR as the sense element instead of the on-board sense resistors to save cost and board space and to improve efficiency.

The LT1952/LT1952-1 are current mode PWM controllers optimized to control the forward converter topology, using one primary MOSFET. The LT1952/LT1952-1 provide synchronous rectifier control, resulting in extremely high efficiency. A programmable Volt-Second clamp provides a safeguard for transformer reset that prevents saturation. This allows a single MOSFET on the primary side to reliably run at greater than 50% duty cycle for high MOSFET, transformer and rectifier utilization. The devices include soft-start for controlled exit from shutdown and undervoltage lockout. A precision 107mV current limit threshold, independent of duty cycle, combines with softstart to provide hiccup short circuit protection. The LT1952 is optimized for micropower bootstrap startup from high input voltages. The LT1952-1 allows startup from lower input voltages. Programmable slope compensation and leading edge blanking allow optimization of loop bandwidth with a wide range of inductors and MOSFETs. Each device can be programmed over a 100kHz to 500kHz frequency range and the part can be synchronized to an external clock. The error amplifier is a true op amp, allowing a wide range of compensation networks. The LT1952/LT1952-1 are available in a small 16-pin SSOP package.Applications Telecommunications Power Supplies Industrial and Distributed Power Isolated and Non-Isolated DC/DC Converters

The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:LTC6954-1: Three LVPECL outputsLTC6954-2: Two LVPECL and one LVDS/CMOS outputsLTC6954-3: One LVPECL and two LVDS/CMOS outputsLTC6954-4: Three LVDS/CMOS outputsEach output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.The LTC6954 also features Linear Technology?s EZSync system for perfect clock synchronization and alignment every time.All device settings are controlled through an SPI-compatible serial port.Applications Clocking High Speed, High Resolution ADCs, DACs?and Data Acquisition Systems Low Jitter Clock Distribution

The AD5371 contains 40 14-bit DACs in a single 80-lead LQFP or 100-ball CSP_BGA. The device provides buffered voltage outputs with a span of 4? the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into five groups of eight DACs. Three offset DACs allow the output range of the groups to be adjusted. Group 0 can be adjusted by Offset DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.The AD5371 offers guaranteed operation over a wide supply range, with VSS from ?16.5 V to ?4.5 V and VDD from 9 V to 16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.The AD5371 has a high speed serial interface that is compatible with SPI, QSPI?, MICROWIRE?, and DSP interface standards and can handle clock speeds of up to 50 MHz. It also has a 100 MHz low voltage differential signaling (LVDS) serial interface.The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register to allow removal of gain and offset errors.Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin.APPLICATIONS Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical switches Industrial control systems Instrumentation

The AD9146 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency.The AD9146 TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 3-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9146 comes in a 48-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Compact LVDS digital interface offers reduced width data bus.APPILICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

The AD9161 is a high performance, 11-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2? interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2? interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode? operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm ? 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm ? 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.Applications Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point Instrumentation, automatic test equipment (ATE) Radars and jammers