Analog Devices Inc.

Category: Miscellaneous

The third generation of SHARC®­ Processors, which includes the ADSP-21375 and ADSP-21371, offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with other SHARC Processors such as the ADSP-21367 and ADSP-21369. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21371 offers a high performance at a very low cost 266 MHz/1596 MFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21371 particularly well suited to address the increasing requirements of the professional and automotive audio market segments while maintaining a low cost. In addition to its higher core performance, the ADSP-21371 includes additional value-added peripherals such as an S/PDIF transmitter/receiver. The ADSP-21371 also provides a direct interface to synchronous SDRAMs with a 32-bit interface that operates at 133 MHz.Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, and S/PDIF Tx/Rx.DEDICATED AUDIO COMPONENTS ADSP-21371—S/PDIF-compatible digital audio receiver/transmitter ADSP-21371—8 dual data line serial ports that operate at up to 33 Mbps on each data line — each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair 16 PWM outputs configured as four groups of four outputs ROM-based security features include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Available in a 208-lead LQFP_EP package

* $40.32 - * $41.47