Analog Devices Inc.

Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

$39.45