TLV9352IDR
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Technical Specifications
| Lead Free Status | Y |
| ROHS Compliance | Y |
| Approx. price(US$) | .105 | 1u |
| Architecture | CMOS |
| CMRR(typ)(dB) | 110 |
| Features | Cost Optimized,EMI Hardened,MUX Friendly |
| GBW(typ)(MHz) | 3.5 |
| Input common mode headroom (to negative supply)(typ)(V) | -0.1 |
| Input common mode headroom (to positive supply)(typ)(V) | 0.1 |
| Iout(typ)(A) | 0.06 |
| Iq per channel(typ)(mA) | 0.65 |
| Number of channels | 2 |
| Offset drift(typ)(V/C) | 1.5 |
| Operating temperature range(C) | -40 |
| Output swing headroom (to negative supply)(typ)(V) | 0.025 |
| Output swing headroom (to positive supply)(typ)(V) | -0.025 |
| Package area(mm^2) | 29.4 |
| Package size (L x W)(mm) | 4.9 x 6 |
| Package type | SOIC |
| Pin count | 8 |
| Rail-to-rail | In to V-,Out |
| Rating | Catalog |
| Slew rate(typ)(V/s) | 20 |
| TI functional safety category | |
| TI package name | D |
| TI.com inventory | 64214 |
| Total supply voltage (+5 V = 5, 5 V = 10)(max)(V) | 40 |
| Total supply voltage (+5 V = 5, 5 V = 10)(min)(V) | 4.5 |
| Vn at 1 kHz(typ)(nVHz) | 15 |
| Vos (offset voltage at 25C)(max)(mV) | 1.8 |