The LTC6948 is a high performance, low noise, 6.39GHz phase-locked loop (PLL) with a fully integrated VCO, including a reference divider, phase-frequency detector (PFD), ultralow noise charge pump, fractional feedback divider, and VCO output divider.The fractional divider uses an advanced, 4th order ?? modulator which provides exceptionally low spurious levels. This allows wide loop bandwidths, producing extremely low integrated phase noise values.The programmable VCO output divider, with a range of 1 through 6, extends the output frequency range.Applications Wireless Basestations (LTE, WiMAX, W-CDMA, PCS) Microwave Data Links Military and Secure Radio Test and Measurement

The LTC1799 is a precision oscillator that is easy to use and occupies very little PC board space. The oscillator frequency is programmed by a single external resistor (RSET). The LTC1799 has been designed for high accuracy operation (?1.5% frequency error) without the need for external trim components.The LTC1799 operates with a single 2.7V to 5.5V power supply and provides a rail-to-rail, 50% duty cycle square wave output. The CMOS output driver ensures fast rise/fall times and rail-to-rail switching. The frequency-setting resistor can vary from 3k to 1M to select a master oscillator frequency between 100kHz and 33MHz (5V supply). The three-state DIV input determines whether the master clock is divided by 1, 10 or 100 before driving the output, providing three frequency ranges spanning 1kHz to 33MHz (5V supply). The LTC1799 features a proprietary feedback loop that linearizes the relationship between RSET and frequency, eliminating the need for tables to calculate frequency.Applications Low Cost Precision Oscillator Switching Power Supply Clock Reference Clocking Switched Capacitor Filters Fixed Crystal Oscillator Replacement Ceramic Oscillator Replacement

The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.The HMC7043 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 can generate up to seven DCLK and SYSREF clock pairs per the JESD204B/JESD204C interface requirements.The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and LVCMOS, and different bias conditions to adjust for varying board insertion losses. One of the unique features of the HMC7043 is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 ? or 100 ? internal and external termination options. The HMC7043 device features an RF SYNC feature that synchronizes multiple HMC7043 devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephrasing the nested HMC7043 or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase. The HMC7043 is offered in a 48-lead, 7 mm ? 7 mm LFCSP package with an exposed pad connected to ground. Applications JESD204B/JESD204C clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Phase array reference distribution Microwave baseband cards

The ADCLK905 (one input, one output), ADCLK907 (dual oneinput, one output), and ADCLK925 (one input, two outputs) areultrafast clock/data buffers fabricated on the Analog Devices, Inc.,proprietary XFCB3 silicon germanium (SiGe) bipolar process.The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).The inputs have center tapped, 100 ?, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.Applications Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking

The ADCLK946 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has a differential input equipped with center-tapped, differential, 100 ? on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.The ADCLK946 features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differen-tial output swing of 1.6 V.The ADCLK946 is available in a 24-lead LFCSP and is specified for operation over the standard industrial temperature range of ?40?C to +85?C.ApplicationsLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation

The ADCLK954 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 ? on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs.The ADCLK954 features 12 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias Vcc to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK954 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of ?40?C to +85?C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

The ADF4377 is a high performance, ultralow jitter, dual output integer-N phased locked loop (PLL) with integrated voltage controlled oscillator (VCO) ideally suited for data converter and mixed signal front end (MxFE) clock applications. The high performance PLL has a figure of merit of -239 dBc/Hz, ultralow 1/f Noise and a high phase frequency detector (PFD) frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4377?s fundamental VCO and output divider generate frequencies from 800 MHz to 12.8 GHz. The ADF4377 integrates all necessary power supply bypass capacitors, saving board space on compact boards.For multiple data converter and MxFE clock applications, the ADF4377 simplifies clock alignment and calibration routines required with other clock solutions, by implementing:automatic reference to output synchronization,extremely well match reference to output delays across process, voltage, and temperature, andsub-ps, jitter free reference to output delay adjustment capability.These features allow for predictable and precise multi-chip clock and SYSREF alignment. JESD204B and JESD204C subclass 1 solutions are supported by pairing the ADF4377 with an integrated circuit(IC) that distributes pairs of reference and SYSREF signals.APPLICATIONSHigh Performance Data Converter and MxFE ClockingWireless infrastructure (MC-GSM, 5G)Test and Measurement

The HMC584LP5(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC584LP5(E) integrates resonators, negative resistance devices, varactor diodes and feature half frequency and divide-by-4 outputs. The VCO?s phase noise performance is excellent over temperature, shock, and process due to the oscillator?s monolithic structure. Power output is +10 dBm typical from a +5V supply voltage. The prescaler and RF/2 functions can be disabled to conserve current if not required. The voltage controlled oscillator is packaged in a leadless QFN 5x5 mm surface mount package, and requires no external matching components.APPLICATIONS Point to Point/Multipoint Radio Test Equipment & Industrial Controls SATCOM Military End-Use

622 Mbps Clock and Data Recovery IC

Clock Drivers & Distribution 800MHz 3-Chan Clock Distribution