CLOCK & TIMING ANALOG DEV KITS;

Microwave Wideband Synthesizer with Integrated VCO Features: RF output frequency range: 62.5 MHz to 32,000 MHz Fractional-N synthesizer and Integer N synthesizer High resolution 39-bit fractional modulus Typical spurious PFD: −90 dBc Integrated rms jitter: 38 fs (1 kHz to 100 MHz) Normalized phase noise floor: −234 dBc/Hz PFD operation to 250 MHz Reference frequency operation to 600 MHz Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x 8,000 MHz to 16,000 MHz output at RF16x 16,000 MHz to 32,000 MHz output at RF32x Lock time approximately 3 ms with automatic calibration Lock time <30 μs with autocalibration bypassed Analog and digital power supplies: 3.3 V VCO power supply: 3.3 V and 5 V RF output mute function 7mm × 7mm, 48-terminal LGA package

Real Time Clock Trickle-Charge Timekeeping Chip

Broadband Analog Time Delay SMT, DC - 24 GHz Features: Very Wide Bandwidth: DC - 24 GHz Continuous Adjustable Delay Range: 70 ps Single-Ended or Differential Operation Adjustable Differential Output Voltage Swing: 170 - 760 mVp-p @ 24 GHz Delay Control Modulation Bandwidth: 10 MHz Single Supply: +3.3V  24 Lead 4x4mm SMT Package: 16mm²

1kHz to 33MHz Resistor Set SOT-23 Oscillator Features: One External Resistor Sets the Frequency Fast Start-Up Time: <1ms 1kHz to 33MHz Frequency Range Frequency Error ≤1.5% 5kHz to 20MHz (TA = 25°C) Frequency Error ≤2% 5kHz to 20MHz (TA = 0°C to 70°C) ±40ppm/°C Temperature Stability 0.05%/V Supply Stability 50% ±1% Duty Cycle 1kHz to 2MHz 50% ±5% Duty Cycle 2MHz to 20MHz 1mA Typical Supply Current 100Ω CMOS Output Driver Operates from a Single 2.7V to 5.5V Supply Low Profile (1mm) SOT-23 (ThinSOT™ Package) AEC-Q100 Qualified for Automotive Applications

Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family Features: LTC6955: 11 Output Buffer LTC6955-1: 10 Buffered Outputs and One ÷2 Output Additive Output Jitter ~45fs RMS (ADC SNR Method) Additive Output Jitter < 5fs RMS (Integration BW = 12kHz to 20MHz, f = 7.5GHz) Eleven Ultralow Noise CML Outputs Parallel Control for Multiple Output Configurations –40°C to 125°C Operating Junction TemperatureRange

Broadband Analog Time Delay SMT, DC - 24 GHz Features: Very Wide Bandwidth: DC - 24 GHz Continuous Adjustable Delay Range: 70 ps Single-Ended or Differential Operation Adjustable Differential Output Voltage Swing: 170 - 760 mVp-p @ 24 GHz Delay Control Modulation Bandwidth: 10 MHz Single Supply: +3.3V  24 Lead 4x4mm SMT Package: 16mm²

MMIC VCO SMT w/ Buffer Amplifier, 3.35 - 3.55 GHz Features: Pout +4.7 dBm Phase Noise: -112 dBc/HZ @ 100 KHz No External Resonator Needed Single Supply: 3V @ 41 mA 50 Ohm Matched & DC Blocked RF I/Os OFN Leadless SMT Package, 16mm2

The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detec-tor), a precision charge pump, and a divider/prescaler. The divider/prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz.A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.Applications Satellite communications Broadband wireless access CATV Instrumentation Wireless LANs

The ADF4252 is a dual fractional-N/integer-N frequencysynthesizer that can be used to implement local oscillators (LO)in the upconversion and downconversion sections of wirelessreceivers and transmitters. Both the RF and IF synthesizersconsist of a low noise digital phase frequency detector (PFD), aprecision charge pump, and a programmable reference divider.The RF synthesizer has a ?-?-based fractional interpolator thatallows programmable fractional-N division. The IF synthesizerhas programmable integer-N counters. A complete phase-lockedloop (PLL) can be implemented if the synthesizer is used withan external loop filter and voltage controlled oscillator (VCO).Control of all the on-chip registers is via a simple 3-wire interface.The device operates with a power supply ranging from 2.7 V to3.3 V and can be powered down when not in use.Applications Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment