1kHz to 33MHz Resistor Set SOT-23 Oscillator Features: One External Resistor Sets the Frequency Fast Start-Up Time: <1ms 1kHz to 33MHz Frequency Range Frequency Error ≤1.5% 5kHz to 20MHz (TA = 25°C) Frequency Error ≤2% 5kHz to 20MHz (TA = 0°C to 70°C) ±40ppm/°C Temperature Stability 0.05%/V Supply Stability 50% ±1% Duty Cycle 1kHz to 2MHz 50% ±5% Duty Cycle 2MHz to 20MHz 1mA Typical Supply Current 100Ω CMOS Output Driver Operates from a Single 2.7V to 5.5V Supply Low Profile (1mm) SOT-23 (ThinSOT™ Package) AEC-Q100 Qualified for Automotive Applications

Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family Features: LTC6955: 11 Output Buffer LTC6955-1: 10 Buffered Outputs and One ÷2 Output Additive Output Jitter ~45fs RMS (ADC SNR Method) Additive Output Jitter < 5fs RMS (Integration BW = 12kHz to 20MHz, f = 7.5GHz) Eleven Ultralow Noise CML Outputs Parallel Control for Multiple Output Configurations –40°C to 125°C Operating Junction TemperatureRange

Broadband Analog Time Delay SMT, DC - 24 GHz Features: Very Wide Bandwidth: DC - 24 GHz Continuous Adjustable Delay Range: 70 ps Single-Ended or Differential Operation Adjustable Differential Output Voltage Swing: 170 - 760 mVp-p @ 24 GHz Delay Control Modulation Bandwidth: 10 MHz Single Supply: +3.3V  24 Lead 4x4mm SMT Package: 16mm²

Microwave Wideband Synthesizer with Integrated VCO Features: RF output frequency range: 62.5 MHz to 32,000 MHz Fractional-N synthesizer and Integer N synthesizer High resolution 39-bit fractional modulus Typical spurious PFD: −90 dBc Integrated rms jitter: 38 fs (1 kHz to 100 MHz) Normalized phase noise floor: −234 dBc/Hz PFD operation to 250 MHz Reference frequency operation to 600 MHz Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x 8,000 MHz to 16,000 MHz output at RF16x 16,000 MHz to 32,000 MHz output at RF32x Lock time approximately 3 ms with automatic calibration Lock time <30 μs with autocalibration bypassed Analog and digital power supplies: 3.3 V VCO power supply: 3.3 V and 5 V RF output mute function 7mm × 7mm, 48-terminal LGA package

CLOCK & TIMING ANALOG DEV KITS;

CLOCK GENERATORS & BUFFERS;

The HMC940LC4B is a 1:4 Fanout Buffer designed to support data transmission rates up to 13 Gbps, and clock frequencies as high as 13 GHz. All differential inputs and outputs are DC coupled and terminated on chip with 50 Ohm resistors to ground. The outputs may be used in either single-ended or differential modes, and should be AC or DC coupled into 50 Ohm resistors connected to ground.The HMC940LC4B also features an output level control pin, VR which allows for loss compensation or for signal level optimization. The HMC940LC4B operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 4×4 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Clock Buffering up to 13 GHz

The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance.The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set.The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features.The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters

The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.The AD9553 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency translations.The AD9553 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9553 is implemented in a strictly CMOS process.The AD9553 operates over the extended industrial temperature range of −40°C to +85°C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON Wireless infrastructure Test and measurement (including handheld devices)

The AD9517-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-0 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-0 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-0 is specified for operation over the industrial range of −40°C to +85°C.Applications Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-0 is used, it is refers to that specific member of the AD9517 family.