The AD9517-11?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-1 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-1 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-1 is specified for operation over the industrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1AD9517 is used throughout the data sheet to refer to all the members of the AD9517 family. However, when AD9517-1 is used, it is refers to that specific member of the AD9517 family.

The AD9530 is a fully integrated PLL and distribution supporting, clock cleanup, and frequency translation device for 40 Gbps/ 100 Gbps OTN applications. The internal PLL can lock to one of two reference frequencies to generate four discrete output frequencies up to 2.7 GHz.The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow noise voltage controlled oscillator (VCO). All four outputs are individually divided down from the internal VCO using two high speed VCO dividers (the Mx dividers) and four individual 8-bit channel dividers (the Dx dividers). The high speed VCO dividers offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of possible output frequencies. The AD9530 is configurable for loop bandwidths <15 kHz to attenuate reference noise.The AD9530 is available in a 48-lead LFCSP and operates from a single 2.5 V typical supply voltage.The AD9530 operates over the extended industrial temperature range of ?40?C to +85?C.?Applications 40 Gbps/100 Gbps optical transport network (OTN) line side clocking Clocking of high speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) Data communications

The AD9549 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed.The AD9549 operates over an industrial temperature range of ?40?C to +85?C.APPLICATIONS Network synchronization Reference clock jitter cleanup SONET/SDH clocks up to OC-192, including FEC Stratum 3/3E reference clocks Wireless base stations, controllers Cable infrastructure Data communications

The AD9550 is a phase-locked loop (PLL) based clock translatordesigned to address the needs of wireline communicationand base station applications. The device employs an integer-NPLL to accommodate the applicable frequency translationrequirements. It accepts a single-ended input reference signalat the REF input.The AD9550 is pin programmable, providing a matrix ofstandard input/output frequency translations from a list of15 possible input frequencies to a list of 51 possible outputfrequency pairs (OUT1 and OUT2).The AD9550 output is compatible with LVPECL, LVDS, orsingle-ended CMOS logic levels, although the AD9550 isimplemented in a strictly CMOS process.The AD9550 operates over the extended industrial temperaturerange of ?40?C to +85?C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Flexible frequency translation for wireline applications such as Ethernet, T1/E1, SONET/SDH, GPON, xDSL Wireless infrastructure Test and measurement (including handheld devices)

The AD9554 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitteroutput clock even when all reference inputs have failed.The AD9554 operates over an industrial temperature range of ?40?C to +85?C. If a smaller device is needed, the AD9554-1 is a version of this device with one output per PLL. If a single or dual DPLL version of this device is needed, refer to the AD9557 or AD9559, respectively.Applications Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure Data communications Professional video

The AD9576 provides a multiple output clock generator function comprising two dedicated phase-locked loop (PLL) cores with flexible frequency translation capability, optimized to serve as a robust source of asynchronous clocks for an entire system, providing extended operating life within frequency tolerance through monitoring of and automatic switchover between redundant crystal (XTAL) inputs with minimized switching, induced transients. The fractional-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance, whereas the integer-N PLL provides general-purpose clocks for use as CPU and field-programmable gate array (FPGA) reference clocks.The AD9576 uses pin strapping to select among a multitude of power-on ready configurations for its 11 output clocks, which require only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (PPRx). These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. These parameters can also be manually configured through a serial port interface (SPI).The AD9576 is packaged in a 64-lead, 9 mm ? 9 mm LFCSP, requiring only a single 2.5 V or 3.3 V supply. The operating temperature range is ?40?C to +85?C.Each OUTx output is differential and contains two pins: OUTx and OUTx. For simplicity, the term OUTx refers to the functional output block containing these two pins..Applications Ethernet line cards, switches, and routers Baseband units SATA and PCI express Low jitter, low phase noise clock generation Asynchronous clock generation

The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.The HMC7043 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 can generate up to seven DCLK and SYSREF clock pairs per the JESD204B/JESD204C interface requirements.The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and LVCMOS, and different bias conditions to adjust for varying board insertion losses. One of the unique features of the HMC7043 is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 ? or 100 ? internal and external termination options. The HMC7043 device features an RF SYNC feature that synchronizes multiple HMC7043 devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephrasing the nested HMC7043 or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase. The HMC7043 is offered in a 48-lead, 7 mm ? 7 mm LFCSP package with an exposed pad connected to ground. Applications JESD204B/JESD204C clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Phase array reference distribution Microwave baseband cards

The HMC1033LP6GE is a low-noise, wide-band 3.3 V clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 25 MHz and 550 MHz range. The HMC1033LP6GE features a low noise Phase Detector (PD) and Delta- Sigma modulator, capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance.The HMC1033LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-162 dBc/Hz) makes the HMC1033LP6GE an ideal source for a variety of applications?such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SER DES) circuits, FPGAs and processors. The HMC1033LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1033LP6GE can be set to either an LVPECL or LVDS compatible mode, with further output swing which makes the device flexible and compatible with a wide variety of signal level requirements. The output can be internally terminated to reduce component count and cost. The outputs could be terminated externally in LVPECL mode using standard methods such as resistors to ground. An Output Mute function allows the user to shut off the outputs, such as may be required for board testing or debugging. The LVPECL/LVDS, amplitude select and Output Mute function are all programmed SPI serial programming.The HMC1033LP6GE is designed to select between a Power Priority or a Performance Priority mode. The Power Priority setting reduces the current consumption of the part, whereas the Performance Priority setting improves the Jitter and Phase Noise performance.The 24 bit Delta-Sigma Modulator further enhances Hittite?s Exact Frequency Mode, which enables users to generate output frequencies with 0 Hz frequency error in many applications.APPLICATIONS 10G/40G/100G Optical Modules,?Transponders, Line Cards OTN and SONET /SDH Applications Data Converters,?Sample Clock Generation Cellular/4G Infrastructure High Frequency Processor/FPGA Clocks Any Frequency Clock Rate Generation Low Jitter SAW Oscillator Replacement DDS Replacement Frequency Translation Frequency Margining

The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a ?-? based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase- locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment

The ADF4155 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter, external voltage controlled oscillator (VCO), and external reference frequency.The ADF4155 is for use with external VCO parts up to an 8 GHz operating frequency. The high resolution programmable modulus allows synthesis of exact frequencies with 0 Hz error.The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to allow the user to generate RF output frequencies as low as 7.8125 MHz.Control of all on-chip registers is through a simple 3-wire interface. The device operates with a nominal power supply of 3.3 V ? 5% and can be powered down when not in use.The ADF4155 is available in a 24-lead, 4 mm ? 4 mm LFCSP package.APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Test equipment Wireless LANs, CATV equipment Clock generation