The AD9549 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed.The AD9549 operates over an industrial temperature range of −40°C to +85°C.APPLICATIONS Network synchronization Reference clock jitter cleanup SONET/SDH clocks up to OC-192, including FEC Stratum 3/3E reference clocks Wireless base stations, controllers Cable infrastructure Data communications

The ADF4356 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz.The ADF4356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4356 also contains hardware and software power-down modes.Applications Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The LTC2956 is a micropower, wide input voltage range, configurable wake-up timer with pushbutton control. It periodically wakes up and turns on a connected system to perform tasks like monitoring temperature or capturing images. After completing the task, the LTC2956 turns the system off to conserve power.The wake-up timer period can be adjusted from 250ms to 39 days using configuration resistors. The system awake time can be controlled by the input pulse at the SLEEP pin or adjusted by the capacitor at the ONMAX pin. The LTC2956 operates over a wide supply input range from 1.5V to 36V. The low 800nA quiescent current suits battery powered applications.The pushbutton input allows the user to shutdown, turn on or reset the wake-up timer. With the timer in shutdown, the quiescent current drops to 300nA. The LTC2956 also provides three status outputs to indicate mode transitions and pushbutton events. Two versions are available for applications requiring either positive or negative enable polarities.Applications Heartbeat Timers Periodic Wake-Up Control Portable and Battery-Powered Equipment Intervalometers Data Acquisition

The AD9522-31 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. The AD9522 is specified for operation over the standard industrialrange of −40°C to +85°C.The AD9520-3 is an equivalent part to the AD9522-3 featuringLVPECL / CMOS drivers instead of LVDS / CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-3 is used, it is referring to that specificmember of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructuresData Sheet, Rev. 0, 10/08

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9559 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557.APPLICATIONS Network synchronization, including Synchronous Ethernet and OTN mapping/de-mapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications

Timers & Support Products Low-Power General Purpose Timer

The LTC6951 is a high performance, low noise, Phase Locked Loop (PLL) with a fully integrated VCO. The low noise VCO uses no external components and is internally calibrated to the correct output frequency with no external system support.The clock generation section provides five outputs based on the VCO prescaler signal with individual dividers for each output. Four outputs feature very low noise, low skew CML logic. The fifth output is low noise LVDS. All outputs can be synchronized and set to precise phase alignment using the programmable delays.Choose the LTC6951-1 if any desired output frequency falls in the ranges 2.5GHz to 2.7GHz, 1.66GHz to 1.8GHz, or 1.25GHz to 1.35GHz. Choose the LTC6951 for all other frequencies.Applications High Performance Data Converter Clocking Wireless Infrastructure Test and Measurement

The ADF4152HV is a 5.0 GHz, fractional-N or integer N frequency synthesizer with an integrated high voltage charge pump. The synthesizer can drive external wideband voltage controlled oscillators (VCOs) directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. The integrated high voltage charge pump simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies.The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.A simple 3-wire interface controls all on-chip registers. The charge pump operates from a power supply ranging from 6.0 V to 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. The ADF4152HV can be powered down when not in use.Applications Wireless infrastructure Microwave point to point/point to multipoint radios Very small aperture terminal (VSAT) radios Test equipment Private land mobile radios

The AD9517-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-3 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-3 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-3 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.

The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems,including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allowreduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdovercircuitry of the AD9554-1 continuously generates a low jitteroutput clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of ?40?C to +85?C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of thisdevice is needed, refer to the AD9557 or AD9559, respectively.Applications Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure? Data communications? Professional video