The ADF4356 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz.The ADF4356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4356 also contains hardware and software power-down modes.Applications Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The ADF4360-5 is a fully integrated integer-N synthesizer andvoltage controlled oscillator (VCO). The ADF4360-5 is designedfor a center frequency of 1300 MHz. In addition, a divide-by-2option is available, whereby the user gets an RF output ofbetween 600 MHz and 700 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.

The ADF4360-6 is a fully integrated integer-N synthesizerand voltage-controlled oscillator (VCO). The ADF4360-6 isdesigned for a center frequency of 1150 MHz. In addition, adivide-by-2 option is available, whereby the user receives an RFoutput of between 525 MHz and 625 MHz.Control of all the on-chip registers is through a simple 3-wireinterface. The device operates with a power supply ranging from3.0 V to 3.6 V and can be powered down when not in use.Applications Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment

The ADF4158 is a 6.1 GHz, fractional-N frequency synthesizer with modulation and waveform generation capability. It contains a 25-bit fixed modulus, allowing subhertz resolution at 6.1 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (?-?) based fractional interpolator to allow programmable fractional-N division. The INT and FRAC registers define an overall N-divider as N = INT + (FRAC/225).The ADF4158 can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. There are also a number of frequency sweep modes available, which generate various waveforms in the frequency domain, for example, sawtooth and triangular waveforms. Sweeps can be set to run automatically, or each step manually triggered by an external pulse. The ADF4158 features cycle slip reduction circuitry, which leads to faster lock times, without the need for modifications to the loop filter.Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications Frequency modulated continuous wave (FMCW) radar Communications test equipment

The ADF4350 allows implementation of fractional-N orinteger-N phase-locked loop (PLL) frequency synthesizersif used with an external loop filter and external referencefrequency.The ADF4350 has an integrated voltage controlled oscillator(VCO) with a fundamental output frequency ranging from2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16circuits allow the user to generate RF output frequencies as lowas 137.5 MHz. For applications that require isolation, the RFoutput stage can be muted. The mute function is both pin- andsoftware-controllable. An auxiliary RF output is also available,which can be powered down if not in use.Control of all the on-chip registers is through a simple 3-wireinterface. The device operates with a power supply rangingfrom 3.0 V to 3.6 V and can be powered down when not in use.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

The HMC704 has been designed for the best phase noise and lowest spurious content possible in an integrated synthesizer. Fabricated in a SiGe BiCMOS process, this Fractional-N frequency synthesizer consists of a very low noise digital phase detector, VCO divider, reference divider and a precision controlled charge pump.Ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster frequency hopping and low micro-phonics. Exact frequency mode with 24-bit fractional modulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for Digital Pre-Distortion systems.The serial interface offers read back capability and is compatible with a wide variety of protocols.Applications Microwave Point-to-Point Radios? Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, WiMAX Communications Test Equipment CATV Equipment Automotive

The HMC910LC4B is a broadband time delay with 0 to 70 ps continuously adjustable delay range. The delay control is linearly monotonic with respect to the control voltage, VDC and the control input has a modulation bandwidth of 600MHz.The device provides a differential output voltage with constant amplitude for single-ended or differential input voltages above the input sensitivity level, while the output voltage swing may be adjusted using the VAC control pin.The HMC910LC4B features internal temperature compensation and bias circuitry to minimize delay variations with temperature. The device also features an enable pin, ENB. All RF input and outputs of the HMC910LC4B are internally terminated with 50 Ohms to Vcc, and may either be AC or DC coupled. Output pins can be connected directly to a 50 Ohm to Vcc terminated system, while DC blocking capacitors must be used if the terminated system input is 50 Ohms to a DC voltage other than Vcc.APPLICATIONS Synchronization of Clock & Data Transponder Design Serial Data Transmission up to 32 Gbps Broadband Test & Measurement RF ATE Applications

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ? VS. The VREF pin provides a level of ? VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is ?40?C to +85?C. APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE

The AD9516-1?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9516-1 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9516-1 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-1 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The AD9520-0 provides a multi-output clock distributionfunction with sub-picosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHzto 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520-0 serial interface supports both SPI and I2C ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.The AD9520-0 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-0.Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.The AD9520-0 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.The AD9520-0 is specified for operation over the standardindustrial range of ?40?C to +85?C. Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures