The HMC704 has been designed for the best phase noise and lowest spurious content possible in an integrated synthesizer. Fabricated in a SiGe BiCMOS process, this Fractional-N frequency synthesizer consists of a very low noise digital phase detector, VCO divider, reference divider and a precision controlled charge pump.Ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster frequency hopping and low micro-phonics. Exact frequency mode with 24-bit fractional modulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for Digital Pre-Distortion systems.The serial interface offers read back capability and is compatible with a wide variety of protocols.Applications Microwave Point-to-Point Radios? Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, WiMAX Communications Test Equipment CATV Equipment Automotive

The HMC910LC4B is a broadband time delay with 0 to 70 ps continuously adjustable delay range. The delay control is linearly monotonic with respect to the control voltage, VDC and the control input has a modulation bandwidth of 600MHz.The device provides a differential output voltage with constant amplitude for single-ended or differential input voltages above the input sensitivity level, while the output voltage swing may be adjusted using the VAC control pin.The HMC910LC4B features internal temperature compensation and bias circuitry to minimize delay variations with temperature. The device also features an enable pin, ENB. All RF input and outputs of the HMC910LC4B are internally terminated with 50 Ohms to Vcc, and may either be AC or DC coupled. Output pins can be connected directly to a 50 Ohm to Vcc terminated system, while DC blocking capacitors must be used if the terminated system input is 50 Ohms to a DC voltage other than Vcc.APPLICATIONS Synchronization of Clock & Data Transponder Design Serial Data Transmission up to 32 Gbps Broadband Test & Measurement RF ATE Applications

The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:LTC6954-1: Three LVPECL outputsLTC6954-2: Two LVPECL and one LVDS/CMOS outputsLTC6954-3: One LVPECL and two LVDS/CMOS outputsLTC6954-4: Three LVDS/CMOS outputsEach output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.The LTC6954 also features Linear Technology?s EZSync system for perfect clock synchronization and alignment every time.All device settings are controlled through an SPI-compatible serial port.Applications Clocking High Speed, High Resolution ADCs, DACs?and Data Acquisition Systems Low Jitter Clock Distribution

The ADF4158 is a 6.1 GHz, fractional-N frequency synthesizer with modulation and waveform generation capability. It contains a 25-bit fixed modulus, allowing subhertz resolution at 6.1 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (?-?) based fractional interpolator to allow programmable fractional-N division. The INT and FRAC registers define an overall N-divider as N = INT + (FRAC/225).The ADF4158 can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. There are also a number of frequency sweep modes available, which generate various waveforms in the frequency domain, for example, sawtooth and triangular waveforms. Sweeps can be set to run automatically, or each step manually triggered by an external pulse. The ADF4158 features cycle slip reduction circuitry, which leads to faster lock times, without the need for modifications to the loop filter.Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications Frequency modulated continuous wave (FMCW) radar Communications test equipment

The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and high frequency programmable feedback dividers (A, B, and P). A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The synthesizer can be used to drive external microwave VCOs via an active loop filter. Its very high bandwidth means a frequency doubler stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the existing?ADF4106/ADF4107/ADF4108 family of devices from Analog Devices, Inc. Their pinouts match very closely with the exception of the ADF41020?s single-ended RF input pin, meaning only a minor layout change is required when updating current designs.Applications Microwave point-to-point/multipoint radios Wireless infrastructure VSAT radios Test equipment Instrumentation

The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.ADF4106-EP Supports defense and aerospace applications (AQEC standard).Applications Broadband wireless access Satellite systems Instrumentation Wireless LANS Base stations for wireless radios

The ADF4113HV is an integer-N frequency synthesizer with a high voltage charge pump (15 V). The synthesizer is designed for use with voltage controlled oscillators (VCOs) that have high tuning voltages (up to 15 V). Active loop filters are often used to achieve high tuning voltages, but the ADF4113HV charge pump can drive a high voltage VCO directly with a passive-loop filter. The ADF4113HV can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision high voltage charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1).A simple 3-wire interface controls all of the on-chip registers. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.

The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. They consist of low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP+A).In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator).Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.

The ADF41513 is an ultralow noise frequency synthesizer that can be used to implement local oscillators (LOs) as high as 26.5 GHz in the upconversion and downconversion sections of wireless receivers and transmitters.The ADF41513 is designed on a high performance silicon geranium (SiGe), bipolar complementary metal-oxide semiconductor (BiCMOS) process, achieving a normalized phase noise floor of ?235 dBc/Hz. The phase frequency detector (PFD) operates up to 250 MHz (integer N mode)/125 MHz (fractional-N mode) for improved phase noise and spur performance. The variable modulus, ?-? modulator allows extremely fine resolution when using a 49-bit divide value. The ADF41513 can be used as an integer N phase-locked loop (PLL), or it can be used as a fractional-N PLL with either a fixed modulus for subhertz frequency resolution or variable modulus for subhertz exact frequency resolution.A complete PLL is implemented when the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The 26.5 GHz bandwidth eliminates the need for a frequency doubler or divider stage, simplifying system architecture and reducing cost. The ADF41513 is packaged in a compact, 24-lead, 4 mm ? 4 mm LFCSPApplications Test equipment and instrumentation Wireless infrastructure Microwave point to point and multipoint radios Very small aperture terminal (VSAT) radios Aerospace and defense

The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer that implements local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a ??? based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.ApplicationsCATV equipmentBase stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA)Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)Wireless LANs, PMRCommunications test equipment