FANOUT BUFFER ROHS COMPLIANT: YES

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture isspecifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes theADF4196 suitable for pulse Doppler radar applications.The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (?-?) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Pulsed Doppler radar Instrumentation and test equipment Beam-forming/phased array systems

Bus Driver, SSTU Series, 1-Func, TTL, PBGA96

Real Time Clock Serial 8-Pin SNT-8A T/R

Z80 Dual Channel Asynchronous Receiver/Transmitter, Package Style:LQFP

CY2304 Series Quad Output 3.3 V 140 MHz PCI-X Buffer Surface Mount - TSSOP-8

Low Skew Clock Driver, 29949 Series, 15 True Output(s), PQFP52

PLL Based Clock Driver, 2308 Series, 8 True Output(s), PDSO16

REEL / Clock Distribution

PLL Based Clock Driver, 2308 Series, 8 True Output(s), PDSO16