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CDC421A100RGET
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Price |
|
$7.10 |
|
$11.25 |
|
$13.66 |
|
$9.64 |
|
|
|
RoHS |
|
Yes |
Yes |
Compliant |
Yes |
Compliant |
Compliant |
Yes |
Yes |
Compliant |
Compliant |
Lead Status |
|
Yes |
Yes |
No |
Yes |
No |
Yes |
Yes |
Yes |
Yes |
No |
Output Frequency(Max)(MHz) |
|
100 |
|
800 |
1100 |
1500 |
280 |
650 |
200 |
800 |
800 |
Package Size |
|
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
VCC Core(V) |
|
3.3 |
|
|
3.3 |
|
3.3 |
|
|
|
|
Operating Temperature Range(C) |
|
-40 to 85 |
|
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
Package Group |
|
VQFN |
TQFP |
BGA,VQFN |
VQFN,WAFERSALE |
VQFN |
SSOP |
VQFN |
VQFN |
VQFN |
VQFN |
No. of Outputs |
|
1 |
12 |
5 |
1 |
10 |
1 |
10 |
10 |
12 |
3 |
VCC Out(V) |
|
3.3 |
|
|
3.3 |
|
3.3 |
1.8 |
1.5,1.8,2.5,2.8 |
2.5 |
3.3 |
Output Frequency(Min)(MHz) |
|
100 |
|
10 |
10 |
0.001 |
|
|
|
|
|
Approx. Price (US$) |
|
7.00 | 1ku |
10.34 | 1ku |
10.00 | 1ku |
7.00 | 1ku |
8.95 | 1ku |
2.95 | 1ku |
6.42 | 1ku |
2.95 | 1ku |
5.00 | 1ku |
5.90 | 1ku |
Input Level |
|
LVCMOS, Crystal |
|
LVCMOS (REF_CLK),LVPECL (VCXO_CLK) |
LVCMOS, Crystal |
LVCMOS,LVDS,LVPECL |
HSTL,LVPECL,LVTTL |
LVDS |
HCSL,LVCMOS,LVDS,LVPECL,SSTL,XTAL |
LVCMOS,LVDS,LVPECL |
LVPECL |
Output Level |
|
LVPECL |
|
LVPECL |
LVDS, LVPECL |
LVCMOS,LVDS,LVPECL |
LVDS,LVPECL,LVTTL |
CML |
LVCMOS |
LVDS |
LVPECL,1-LVCMOS No of outputs = 3 LVPECL,LVCMOS |
Operating Frequency Range(Min)(MHz) |
|
|
25 |
|
|
|
|
|
|
|
|
Rating |
|
|
Catalog |
Catalog |
|
Catalog |
|
Catalog |
Catalog |
Catalog |
Catalog |
t(phase error)(ps) |
|
|
500 |
|
|
|
|
|
|
|
|
tsk(o)(ps) |
|
|
500 |
|
|
|
|
|
|
|
|
Operating Frequency Range(Max)(MHz) |
|
|
100 |
|
|
|
|
|
|
|
|
VCC(V) |
|
|
3.3 |
|
|
|
|
1.8 |
|
2.5 |
3.3 |
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)(ps) |
|
|
200 |
|
|
|
|
|
|
|
|
Number of Inputs |
|
|
|
1 |
|
2 |
|
|
|
|
|
Divider Ratio |
|
|
|
1 to 16 |
|
1 to 80 |
|
|
|
|
|
Supply Voltage(Max)(V) |
|
|
|
3.6 |
|
3.6 |
|
|
|
|
|
Supply Voltage(Min)(V) |
|
|
|
3 |
|
3 |
|
|
|
|
|
Special Features |
|
|
|
OPAMP for Active Loop Filter,Programmable Delay |
Design Tool Available |
Integrated EEPROM,Programmable Phase Offset |
Spread Spectrum Clocking (SSC),3.3V Vcc/Vdd |
|
|
|
|
Programmability |
|
|
|
|
EEPROM, Serial Interface |
|
Pin configuration |
|
|
|
|
Additive RMS Jitter(Typ)(fs) |
|
|
|
|
|
|
|
40 |
25 |
171 |
150 |
Input Frequency(Max)(MHz) |
|
|
|
|
|
|
|
650 |
200 |
800 |
800 |