The AD5684, a member of the nanoDAC+™ family, is a low power, quad, 12-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5684 also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5684 employs a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL): ±1 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5684R nanoDAC+™ is a quad, 12-bit, rail-to-rail, voltage output DAC. The device includes a 2.5V, 2ppm/˚C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5V (gain=1) or 5V (gain=2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design and exhibits less than 0.1% FSR gain error and 1.5mV offset error performance. The device is available in a 3mm X 3mm LFCSP and a TSSOP package.The AD5684R also incorporates a power-on-reset circuit and a RSTSEL pin that ensures the DAC outputs power up to zero-scale or midscale, and remain there until a valid write takes place. Each device contains a per-channel power-down feature that reduces the current consumption of the device to 4 uA at 3 V while in power-down mode.The AD5684R employs a versatile SPI interface that operates at clock rates up to 50 MHz and includes a VLOGIC pin intended for 1.8V/3V/5V logic.Product Highlights High relative accuracy: AD5684R (12-bit): ±1LSB INL max Low drift on-chip reference: 2.5V, 2ppm/°C temperature drift Two package options: 3mm × 3mm 16-lead LFCSP or 16-lead TSSOPApplications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5689/AD5687 members of the nanoDAC+™ family arelow power, dual, 16-/12-bit, buffered voltage output digital-to-analogconverters (DACs). The devices include a gain select pingiving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). TheAD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, areguaranteed monotonic by design, and exhibit less than 0.1% FSRgain error and 1.5 mV offset error performance. Both devices areavailable in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5689/AD5687 also incorporate a power-on reset circuitand a RSTSEL pin that ensures that the DAC outputs power upto zero scale or midscale and remain there until a valid writetakes place. Each part contains a per channel power-down featurethat reduces the current consumption of the device to 4 µA at3 V while in power-down mode.The AD5689/AD5687 uses a versatile serial peripheral interfacethat operates at clock rates up to 50 MHz. Both devices containa VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5689 (16-bit): ±2 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options. 3 mm × 3 mm, 16-lead LFCSP or 16-lead TSSOPApplications Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5693R / AD5692R / AD5691R / AD5693, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage output DACs. The devices, except the AD5693,include an enabled by default internal 2.5 V reference, offering2 ppm/°C drift. The output span can be programmed to be 0 V toVREF or 0 V to 2 × VREF. All devices operate from a single 2.7 V to5.5 V supply and are guaranteed monotonic by design. Thedevices are available in a 2.00 mm × 2.00 mm, 8-lead LFCSP ora 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. The AD5693R / AD5692R /  AD5691R / AD5693 contain a power-down mode that reduces thecurrent consumption of the device to 2 μA (maximum) at 5 V andprovides software selectable output loads.The AD5693R / AD5692R / AD5691R / AD5693 use an I2Cinterface. Some device options also include an asynchronousRESET pin and a VLOGIC pin, allowing 1.8 V compatibility.Product Highlights High relative accuracy (INL): ±2 LSB maximum (AD5693R/AD5693, 16-bit). Low drift, 2.5 V on-chip reference: 2 ppm/°C typical and 5 ppm/°C maximum temperature coefficient. 2 mm × 2 mm, 8-lead LFCSP and 10-lead MSOP. Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources Optical modules

The AD5693R / AD5692R / AD5691R / AD5693, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage output DACs. The devices, except the AD5693,include an enabled by default internal 2.5 V reference, offering2 ppm/°C drift. The output span can be programmed to be 0 V toVREF or 0 V to 2 × VREF. All devices operate from a single 2.7 V to5.5 V supply and are guaranteed monotonic by design. Thedevices are available in a 2.00 mm × 2.00 mm, 8-lead LFCSP ora 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. The AD5693R / AD5692R /  AD5691R / AD5693 contain a power-down mode that reduces thecurrent consumption of the device to 2 μA (maximum) at 5 V andprovides software selectable output loads.The AD5693R / AD5692R / AD5691R / AD5693 use an I2Cinterface. Some device options also include an asynchronousRESET pin and a VLOGIC pin, allowing 1.8 V compatibility.Product Highlights High relative accuracy (INL): ±2 LSB maximum (AD5693R/AD5693, 16-bit). Low drift, 2.5 V on-chip reference: 2 ppm/°C typical and 5 ppm/°C maximum temperature coefficient. 2 mm × 2 mm, 8-lead LFCSP and 10-lead MSOP. Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources Optical modules

The AD5694, a member of the nanoDAC+™ family, is a low power, quad, 16-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 0V to VREF (gain = 1) or 0V to 2.VREF (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.The AD5696 incorporates a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 µA at 3 V.The AD5696 uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). (12-bit): ±1 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5694R is a low power, quad, 16-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5694R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5694R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5694R (12-bit): ±1 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 3 mm × 3 mm, 16-lead LFCSP. 16-lead TSSOP.Applications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5696, a member of the nanoDAC+™ family, is a low power, quad, 16-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 0V to VREF (gain = 1) or 0V to 2VREF (gain = 2) The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.The AD5696 incorporates a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 µA at 3 V.The AD5696 uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Hightlights High Relative Accuracy (INL): ±2 LSB maximum Excellent DC Performance: Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5697R, a member of the nanoDAC+™ family, is a low power,dual, 12-bit buffered voltage output digital-to-analog converter(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference(enabled by default) and a gain select pin giving a full-scale outputof 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates froma single 2.7 V to 5.5 V supply, is guaranteed monotonic by design,and exhibits less than 0.1% FSR gain error and 1.5 mV offseterror performance. The device is available in a 3 mm × 3 mmLFCSP and a TSSOP package.The AD5697R also incorporates a power-on reset circuit and aRSTSEL pin that ensure that the DAC outputs power up to zeroscale or midscale and remain there until a valid write takesplace. It contains a per channel power-down feature that reducesthe current consumption of the device to 4 µA at 3 V while inpower-down mode.The AD5697R uses a versatile 2-wire serial interface that operatesat clock rates up to 400 kHz and includes a VLOGIC pin intendedfor 1.8 V/3 V/5 V logic.Product Highlights Precision DC Performance. TUE: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOPApplications Base station power amplifiers Process controls (programmable logic controller [PLC] I/O cards) Industrial automation Data acquisition systems

The AD7228A contains eight 8-bit voltage-mode digital-to-analog converters, with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve full specified performance for the part.Separate on-chip latches are provided for each of the eight D/A converters. Data is transferred into the data latches through a common 8-bit TTL/CMOS (5 V) compatible input port. Address inputs A0, A1 and A2 determine which latch is loadedwhen WR goes low. The control logic is speed compatible withmost 8-bit microprocessors.Specified performance is guaranteed for input reference voltages from +2 to +10 V when using dual supplies. The part is also specified for single supply +15 V operation using a reference of +10 V and single supply +5 V operation using a reference of +1.23 V. Each output buffer amplifier is capable of developing+10 V across a 2 kΩ load.The AD7228A is fabricated on an all ion-implanted, high-speed, Linear Compatible CMOS (LC2MOS) process which has been specifically developed to integrate high-speed digital logic circuits and precision analog circuits on the same chip.Product Highlights Eight DACs and Amplifiers in Small Package The single-chip design of eight 8-bit DACs and amplifiers allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all analog inputs and outputs at one side of the package and all digital inputs at the other. Single or Dual Supply Operation The voltage-mode configuration of the DACs allows single supply operation of the AD7228A. The part can also be operated with dual supplies giving enhanced performance for some parameters. Microprocessor Compatibility The AD7228A has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered and speed compatible with most high performance 8-bit microprocessors.