ADC 14BIT 400KSPS PARALLEL WSOIC-28; Resolution (Bits):14bit; Sampling Rate:400kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; ADC / DAC Case Style:WSOIC; No. of Pins:28Pins; Input Channel Type:-; Data Interface:Parallel; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Each; Product Range:Single 14-Bit SAR ADCs; Automotive Qualification Standard:-; MSL:MSL 1 - Unlimited; SVHC:No SVHC (20-Jun-2016)

Complete 12-Bit, 10.0 MSPS Monolithic A/D Converter Features: Monolithic 12-Bit A/D Converter Product Family Family Members are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and 10 MSPS Low Power Dissipation: 59 mW, 100 mW, and 250 mW Single +5 V Supply Integral Nonlinearity Error: 0.5 LSB Differential Nonlinearity Error: 0.3 LSB 70 dB SNR and 86 dB SFDR Out-of-Range Indicator 28-SOIC and 28-SSOP

Analog to Digital Converters - ADC DATA-ACQUISITION SYSTEM

Analog to Digital Converters - ADC 12 bit 105msps low pwr quad ADC

Digital to Analog Converters - DAC 2.7V to 5.5V 8-Bit SPI nanoDAC

Data Acquisition ADCs/DACs - Specialised 8 ARC MIN MIL TEMP R/D IC

Digital to Analog Converters - DAC MULTIPLYING DAC IC

Digital to Analog Converters - DAC Single 3V 12bit SPI DAC with reference

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment