|
|
Texas Instruments
TLC3544CPWG4
|
Texas Instruments
AMC1303E2510DWV
|
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TLC5628IDWG4
|
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TLC2543CDB
|
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TLC0834CDG4
|
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TLV5638IDG4
|
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TLV5616CDG4
|
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DAC5573IPWG4
|
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AMC1306E05DWV
|
Texas Instruments
DAC8831ICDG4
|
| Price |
|
|
|
|
|
|
|
|
|
|
|
| RoHS |
|
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
| Lead Status |
|
No |
No |
No |
No |
No |
No |
No |
No |
No |
No |
| Digital Supply(Min)(V) |
|
|
2.7 |
|
|
|
|
|
|
2.7 |
|
| SNR(dB) |
|
|
85 |
|
|
|
|
|
|
82 |
|
| # Input Channels |
|
|
1 |
|
|
|
|
|
|
1 |
|
| Rating |
|
|
Catalog |
|
|
|
|
|
|
Catalog |
Catalog |
| Analog Voltage AVDD(Min)(V) |
|
|
3 |
|
|
|
|
|
|
3 |
|
| Sample Rate (max)(SPS) |
|
|
10MSPS |
|
|
|
|
|
|
21MSPS |
|
| Operating Temperature Range(C) |
|
|
-40 to 125 |
|
|
|
|
|
|
-40 to 125 |
-40 to 85 |
| Power Consumption(Typ)(mW) |
|
|
28.7 |
|
|
|
|
|
|
45 |
0.015 |
| Package Size |
|
|
mm2 |
|
|
|
|
|
|
mm2 |
mm2 |
| Package Group |
|
|
SOIC |
|
|
|
|
|
|
SOIC |
SOIC,VQFN |
| Analog Voltage AVDD(Max)(V) |
|
|
5.5 |
|
|
|
|
|
|
5.5 |
|
| Interface |
|
|
Serial CMOS |
|
|
|
|
|
|
Serial CMOS |
SPI |
| Isolation(kV peak) |
|
|
7 |
|
|
|
|
|
|
7 |
|
| Architecture |
|
|
Delta-Sigma |
|
|
|
|
|
|
Delta-Sigma |
|
| Digital Supply(Max)(V) |
|
|
5.5 |
|
|
|
|
|
|
5.5 |
|
| CMTI(Min)(kV/s) |
|
|
50 |
|
|
|
|
|
|
50 |
|
| SFDR(dB) |
|
|
98 |
|
|
|
|
|
|
83 |
|
| Approx. Price (US$) |
|
|
2.90 | 1ku |
|
|
|
|
|
|
|
6.25 | 1ku |
| INL(Max)(+/-LSB) |
|
|
4 |
|
|
|
|
|
|
4 |
1 |
| THD(Max)(dB) |
|
|
-86 |
|
|
|
|
|
|
-85 |
|
| Input Range(Vp-p) |
|
|
250 mV |
|
|
|
|
|
|
50 mV |
|
| Sample Rate(Max)(MSPS) |
|
|
10 |
|
|
|
|
|
|
21 |
|
| SINAD(dB) |
|
|
|
|
|
|
|
|
|
81.9 |
|
| Output Range Max.(mA/V) |
|
|
|
|
|
|
|
|
|
|
5.5 |
| Offset Error(Max)(%) |
|
|
|
|
|
|
|
|
|
|
N/A |
| Settling Time(s) |
|
|
|
|
|
|
|
|
|
|
1 |
| Resolution(Bits) |
|
|
|
|
|
|
|
|
|
|
16 |
| Output Type |
|
|
|
|
|
|
|
|
|
|
Unbuffered Voltage |
| Special Features |
|
|
|
|
|
|
|
|
|
|
N/A |
| DAC Channels |
|
|
|
|
|
|
|
|
|
|
1 |
| Zero Code Error(Typ)(mV) |
|
|
|
|
|
|
|
|
|
|
1 |
| Sample / Update Rate(MSPS) |
|
|
|
|
|
|
|
|
|
|
2 |
| Output Range Min.(mA/V) |
|
|
|
|
|
|
|
|
|
|
-5.5 |
| Code to Code Glitch(Typ)(nV-sec) |
|
|
|
|
|
|
|
|
|
|
35 |
| Reference |
|
|
|
|
|
|
|
|
|
|
Type |
| Gain Error(Max)(%FSR) |
|
|
|
|
|
|
|
|
|
|
0.01 |
| DAC Architecture |
|
|
|
|
|
|
|
|
|
|
R-2R |
