18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

16-Bit, 105Msps ADC Features: Sample Rate: 105Msps/80Msps 78.2dBFS Noise Floor 100dB SFDR SFDR >82dB at 250MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer Single 3.3V Supply Power Dissipation: 900mW/725mW Optional Clock Duty Cycle Stabilizer Out-of-Range Indicator Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) 40Msps: LTC2204 (16-Bit) 25Msps: LTC2203 (16-Bit) Single-Ended Clock 10Msps: LTC2202 (16-Bit) Single-Ended Clock 48-Pin 7mm × 7mm QFN Package

16-Bit, 105Msps Serial Output ADC (JESD204) Features: High Speed Serial Interface (JESD204) Sample Rate: 105Msps 77.7dBFS Noise Floor 100dB SFDR SFDR >82dB at 250MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Single 3.3V Supply Power Dissipation: 1300mW Clock Duty Cycle Stabilizer Pin Compatible Family 105Msps: LTC2274 80Msps: LTC2273 65Msps: LTC2272 40-Pin 6mm × 6mm QFN Package

Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/C Reference Features: Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2631-L) 4.096V Full-Scale 10ppm/°C (LTC2631-H) Maximum INL Error: 1LSB (LTC2631A-12) Bidirectional Reference: Input or 10ppm/°C Output 400kHz I2C Interface Nine Selectable Addresses (LTC2631-Z) Low Noise (0.7mVP-P , 0.1Hz to 200kHz) Guaranteed Monotonic Over Temperature 2.7V to 5.5V Supply Range (LTC2631-L) Low Power Operation: 180μA at 3V Power Down to 1.8μA Maximum (C and I Grades) Power-On Reset to Zero or Mid-Scale Options Double-Buffered Data Latches Guaranteed Operation From –40°C to 125°C (H-Grade) 8-Lead TSOT-23 (ThinSOT™) Package

16-/14-/11-Bit 2.5Gsps DACs Features:80dBc SFDR at 70MHz fOUT>68dBc SFDR from DC to 1000MHz fOUT40mA Nominal Full-Scale, ±1V Output Compliant10mA to 60mA Adjustable Full-Scale Current RangeSingle or Dual Port DDR LVDS and DHSTL InterfaceLow Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port)>78dBc 2-Tone IMD from DC to 1000MHz fOUT–165dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT170-Lead (9mm × 15mm) BGA Package

16-/14-/11-Bit 2.7Gsps DACs Features:80dBc SFDR at 50MHz fOUT>68dBc SFDR from DC to 1080MHz fOUT40mA Nominal Full-Scale, ±1V Output Compliant10mA to 60mA Adjustable Full-Scale Current RangeSingle or Dual Port DDR LVDS and DHSTL InterfaceLow Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port)>78dBc 2-Tone IMD from DC to 1000MHz fOUT–156dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT170-Lead (9mm × 15mm) BGA Package

16-/14-/11-Bit 2.7Gsps DACs Features:80dBc SFDR at 50MHz fOUT>68dBc SFDR from DC to 1080MHz fOUT40mA Nominal Full-Scale, ±1V Output Compliant10mA to 60mA Adjustable Full-Scale Current RangeSingle or Dual Port DDR LVDS and DHSTL InterfaceLow Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port)>78dBc 2-Tone IMD from DC to 1000MHz fOUT–156dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT170-Lead (9mm × 15mm) BGA Package

18-Bit, 15Msps SAR ADC Features:15Msps Throughput RateNo Pipeline Delay, No Cycle Latency95.7dB SNR (Typ) at fIN = 1MHz102dB SFDR (Typ) at fIN = 1MHzNyquist Sampling Up to 7.5MHz InputGuaranteed 18-Bit, No Missing Codes±3LSB INL (Max)8.192VP-P Differential Inputs5V and 2.5V SuppliesInternal 20ppm/°C (Max) ReferenceSerial LVDS Interface125mW Power Dissipation32-Pin (5mm × 5mm) QFN Package

14-Bit, 80Msps Ultra-Low Power 1.8V ADCs Features: 73.4dB SNR 85dB SFDR Low Power: 127mW/106mW/89mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

12-Bit, 105Msps Ultralow Power 1.8V ADCs Features: 70.8dB SNR 85dB SFDR Low Power: 124mW/103mW/87mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package