Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP

Robust, Triple Ch. Isolator W/ Output Enable & 0 Reverse Channels Features: High common-mode transient immunity: 100 kV/µs High robustness to radiated and conducted noise Low propagation delay 13 ns maximum for 5 V operation 15 ns maximum for 1.8 V operation 150 Mbps maximum guaranteed data rate Backward compatibility ADuM130E1/ADuM131E1 pin compatible with ADuM1300/ADUM1301 Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C Fail-safe high or low options 16-lead, RoHS compliant, SOIC package See data sheet for additional information

12-Bit High Speed Multiplying D/A Converter Features: Differential Nonlinearity: ±1/2 LSB Nonlinearity: 0.05% Fast Settling Time: 250 ns High Compliance: -5 V to +10 V Differential Outputs: 0 to 4 mA Guaranteed Monotonicity: 12 bits Low Full-Scale Tempco: 10 ppm/°C Circuit Interface to TTL, CMOS, ECL, PMOS/NMOS Low Power Consumption: 225 mW Industry Standard AM6012 Pinout Available in Die Form

Quad 8-Bit Multiplying CMOS D/A Converter with Memory Features: Four DACs in a 28 Pin, 0.6 Inch Wide DIP or 28-Pin JEDEC Plastic Chip Carrier ±1/4 LSB Endpoint Linearity Guaranteed Monotonic DACs Matched to Within 1% Microprocessor Compatible Read/Write Capability (with Memory) TTL/CMOS Compatible Four-Quadrant Multiplication Single-Supply Operation (+5 V) Low Power Consumption Latch-Up Resistant Available in Die Form

16-Bit, Serial, 100 kSPS Sampling ADC. Features: Autocalibrating On-Chip Sample-Hold Function Serial Output 16 Bits No Missing Codes ±1 LSB INL –99 dB THD 92 dB S/(N+D) 1 MHz Full Power Bandwidth

2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit nanoDAC in 10-lead LFCSP, 16-lead 3 mm x 3 mm LFCSP, and 16-lead TSSOP Features: 12-/16-bit resolution 1 LSB INL 11.8 nV/√Hz noise spectral density 1 μs settling time 1.1 nV-sec glitch energy 0.05 ppm/°C temperature drift 5 kV HBM ESD classification See data sheet for additional features Also available in16-lead TSSOP

Low Cost 10-Bit Monolithic D/A Converter Features: Complete Current Output Converted High Stability Buried Zener Reference Laser Trimmed to High Accuracy (1/4 LSB Max Error, AD561K, T) Trimmed Output Application Resistors for 0 V to +10 V, ±5 V Ranges Fast Settling - 250 ns to 1/2 LSB Guaranteed Monotonocity Over Full Operating Temperature Range TTL/DTL and CMOS Compatible (Positive True Logic) Single Chip Monolithic Construction Available in Chip Form MIL-STD-883-Compliant Versions Available

12 Channel, 8-Bit TrimDACs with Power Shutdown & Separate VREFL Input Features: Low Cost Replaces 12 Potentiometers Individually Programmable Outputs Power Shutdown < 55 µWatts Including IDD & IREF 3-Wire SPI Compatible Serial Input Midscale Preset, AD8802 Separate VREF Range Settling, AD8804 +3 to +5 Single Supply Operation

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment