16-Bit, 105Msps ADC Features: Sample Rate: 105Msps/80Msps 78.2dBFS Noise Floor 100dB SFDR SFDR >82dB at 250MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer Single 3.3V Supply Power Dissipation: 900mW/725mW Optional Clock Duty Cycle Stabilizer Out-of-Range Indicator Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) 40Msps: LTC2204 (16-Bit) 25Msps: LTC2203 (16-Bit) Single-Ended Clock 10Msps: LTC2202 (16-Bit) Single-Ended Clock 48-Pin 7mm × 7mm QFN Package

Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/C Reference Features: Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2631-L) 4.096V Full-Scale 10ppm/°C (LTC2631-H) Maximum INL Error: 1LSB (LTC2631A-12) Bidirectional Reference: Input or 10ppm/°C Output 400kHz I2C Interface Nine Selectable Addresses (LTC2631-Z) Low Noise (0.7mVP-P , 0.1Hz to 200kHz) Guaranteed Monotonic Over Temperature 2.7V to 5.5V Supply Range (LTC2631-L) Low Power Operation: 180μA at 3V Power Down to 1.8μA Maximum (C and I Grades) Power-On Reset to Zero or Mid-Scale Options Double-Buffered Data Latches Guaranteed Operation From –40°C to 125°C (H-Grade) 8-Lead TSOT-23 (ThinSOT™) Package

14-Bit, 80Msps Ultra-Low Power 1.8V ADCs Features: 73.4dB SNR 85dB SFDR Low Power: 127mW/106mW/89mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

12-Bit, 105Msps Ultralow Power 1.8V ADCs Features: 70.8dB SNR 85dB SFDR Low Power: 124mW/103mW/87mW Single 1.8V Supply CMOS, DDR CMOS or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full-Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

+5 Volt, Serial Input, Dual 12-Bit DAC Features: Complete Dual 12-Bit DAC No External Components +5 Single-Supply Operation ±10% 4.095 V Full Scale (1 mV/LSB) Buffered Voltage Outputs Low Power: 5 mW/DAC Space Saving 1.5mm Height SO-14 Package

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch