The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing widebandsignals from dc up to 3.0 GHz. Its DAC core features a quad-switch architecture that provides exceptionally low distortion performance with an industry-leading direct RF synthesiscapability. This feature enables multicarrier generation up to the Nyquist frequency in baseband mode as well as second andthird Nyquist zones in mix mode. The output current can be programmed over the 8.66 mA to 31.66 mA range.The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies thedigital interface with existing FGPA/ASIC technology. On-chipcontrollers are used to manage external and internal clock domainvariations over temperature to ensure reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readbackof status registers.The AD9739 is manufactured on a 0.18 μm CMOS process andoperates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ballchip scale ball grid array for reduced package parasitics.Product Highlights Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix mode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. A multichip synchronization capability. Programmable differential current output with an 8.66 mA to 31.66 mA range.Applications Broadband communications systems  Military jammers Instrumentation, automatic test equipment  Radar, avionics

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC.The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.Product Highlights Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block. Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR). Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.Applications Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless

The ADAS1000 measures electrocardiac (ECG) signals, thoracic impedance, pacing artifacts,and lead-on/lead-off status and output this information in theform of a data frame supplying either lead/vector or electrodedata at programmable data rates. Its low power and small sizemake it suitable for portable, battery-powered applications.The high performance also makes it suitable for higher enddiagnostic machines. The ADAS1000 is a full-featured, 5-channel ECG includingrespiration and pace detection, while the ADAS1000-1 offersonly ECG channels with no respiration or pace features. Similarly,the ADAS1000-2 is a subset of the main device and is configuredfor gang purposes with only the ECG channels enabled (norespiration, pace, or right leg drive).The ADAS1000/ADAS1000-1/ADAS1000-2 are designed tosimplify the task of acquiring and ensuring quality ECG signals.They provide a low power, small data acquisition system forbiopotential applications. Auxiliary features that aid in betterquality ECG signal acquisition include multichannel averageddriven lead, selectable reference drive, fast overload recovery,flexible respiration circuitry returning magnitude and phaseinformation, internal pace detection algorithm operating onthree leads, and the option of ac or dc lead-off detection. Severaldigital output options ensure flexibility when monitoring andanalyzing signals. Value-added cardiac post processing isexecuted externally on a DSP, microprocessor, or FPGA.Because ECG systems span different applications, theADAS1000/ADAS1000-1/ADAS1000-2 feature a power/noisescaling architecture where the noise can be reduced at theexpense of increasing power consumption. Signal acquisitionchannels can be shut down to save power. Data rates can bereduced to save power.To ease manufacturing tests and development as well as offerholistic power-up testing, the ADAS1000/ADAS1000-1/ADAS1000-2 offer a suite of features, such as dc and ac testexcitation via the calibration DAC and cyclic redundancy check(CRC) redundancy testing, in addition to readback of allrelevant register address space.The input structure is a differential amplifier input, therebyallowing users a variety of configuration options to best suittheir application.The ADAS1000/ADAS1000-1/ADAS1000-2 are available in twopackage options, a 56-lead LFCSP package and a 64-lead LQFPpackage. Both packages are specified over a −40°C to +85°Ctemperature range. APPLICATIONSECG: Monitor & Diagnostic Bedside Patient Monitoring Portable Telemetry Holter AED Cardiac Defibrillators Ambulatory Monitors Pace Maker Programmer Patient Transport Stress testing

The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. LVCMOS Clock Input. High speed, single-ended LVCMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V. APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power,small size, and ease of use. Operating at a conversion rate of up to 65 MSPS, it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock forthe appropriate LVDS serial data rate. A data clock (DCO)for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channelpower-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It isspecified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small package. Low Power of 100 mW per Channel at 65 MSPS. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9222 (12-bit) and AD9252 (14-bit).APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment

The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.The AD9251 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).PRODUCT HIGHLIGHTS The AD9251 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9251 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

The AD9261 is a 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta (Σ-Δ) architecture that achieves 86 dB of dynamic range over a 10 MHz input bandwidth. The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components.The AD9261 has a resistive input impedance that significantly relaxes the requirements of the driver amplifier. In addition, a 32× oversampled 5th-order continuous time loop filter significantly attenuates out of band signals and aliases, reducing the need for external filters at the input.An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate between 30 MSPS to 160 MSPS, enabling a more efficient and direct interface.The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic.The AD9261 operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 375 mW. The AD9261 is available in a 48-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C).Product Highlights Continuous time Σ-Δ architecture efficiently achieves high dynamic range and wide bandwidth. Passive input structure reduces or eliminates the requirements for a driver amplifier. An oversampling ratio of 32× and high order loop filter provide excellent alias rejection reducing or eliminating the need for antialiasing filters. An integrated decimation filter, sample rate converter, PLL clock multiplier, and voltage reference provide ease of use. Operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply. A standard serial port interface (SPI) supports various product features and functions.Applications Data Acquisition Automated Test Equipment Instrumentation Medical Imaging

The AD9704/AD9705/AD9706/AD9707 are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI®) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTS Pin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package). Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding. Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate. Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability. Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference. Industry-Standard 32-Lead LFCSP Package.

The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,high dynamic range TxDAC® devices, respectively, that providea sample rate of 800 MSPS, permitting multicarrier generationup to the Nyquist frequency. Features are included for optimizingdirect conversion transmit applications, including complexdigital modulation, as well as gain, phase, and offset compensation.The DAC outputs are optimized to interface seamlesslywith analog quadrature modulators, such as the ADL5375family from Analog Devices, Inc. A serial peripheral interface(SPI) provides for programming and readback of many internalparameters. Full-scale output current can be programmed overa range of 10 mA to 30 mA. The AD9785/AD9787/AD9788family is manufactured on a 0.18 μm CMOS process and operatesfrom 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFPpackage.Product Highlights Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. Proprietary DAC output switching technique enhances dynamic performance. CMOS data input interface with adjustable setup and hold. Low power complex 32-bit numerically controlled oscillators (NCOs).Applications Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM Digital high or low IF synthesis Transmit diversity Wideband communications LMDS/MMDS, point-to-point

The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,high dynamic range TxDAC® devices, respectively, that providea sample rate of 800 MSPS, permitting multicarrier generationup to the Nyquist frequency. Features are included for optimizingdirect conversion transmit applications, including complexdigital modulation, as well as gain, phase, and offset compensation.The DAC outputs are optimized to interface seamlesslywith analog quadrature modulators, such as the ADL5375family from Analog Devices, Inc. A serial peripheral interface(SPI) provides for programming and readback of many internalparameters. Full-scale output current can be programmed overa range of 10 mA to 30 mA. The AD9785/AD9787/AD9788family is manufactured on a 0.18 μm CMOS process and operatesfrom 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFPpackage.Product Highlights Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. Proprietary DAC output switching technique enhances dynamic performance. CMOS data input interface with adjustable setup and hold. Low power complex 32-bit numerically controlled oscillators (NCOs).Applications Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM Digital high or low IF synthesis Transmit diversity Wideband communications LMDS/MMDS, point-to-point