8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

3-Channel Sigma-Delta ADC with SPI Features: One (ADE7903) 24-bit, Σ-Δ ADC (simultaneously sampling with three ADE7912/ADE7913 ADCs) On-chip temperature sensor 4-wire SPI serial interface Standalone 24-bit, Σ-Δ ADC Up to four ADE7903 and ADE7912/ADE7913 devices clocked from a single crystal or an external clock Synchronization of multiple ADE7903 and ADE7912/ADE7913 devices ±31.25 mV peak input range for current channel ±500 mV peak input range for voltage channels Single 3.3 V supply 20-lead, wide body SOIC package Operating temperature: −40°C to +85°C

Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech and Telephony Features: 16-Bit A/D Converters 16-Bit D/A Converters Programmable Input/Output Sample Rates 75 dB ADC SNR 70 db DAC SNR 64 ksps Maximum Sample Rate -90 db Crosstalk Programmable Input/Output Gain Low group Delay (25 µs per ADC ch, 50 µs per DAC ch) Flexible Serial Port Allows Up to 4 Codecs To Be Connected in Cascade Giving 8 I/O Channels Single 2.7 V to 3.3 V Supply Operation 50 mW Max Power Dissipation at 2.7 V 20-Lead SOIC/SSOP/TSSOP Packages

Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock See data sheet for additional features

Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors Features:Pin-programmable output rateOutput data rate: 10 Hz, 50 Hz, 60 Hz, 120 HzPin-programmable PGAGain: 1, 8, 64, 128Pin-programmable power-down and resetRMS noise: 15 nV @ 10 Hz (gain = 128)Up to 21.5 noise free bits (gain = 1)Please see data sheet for additional features

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter Features: SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Excellent Linearity DNL = ±0.3 LSB typical INL = ±0.7 LSB typical CMOS outputs Single data port at up to 250 MHz Interleaved dual port @ 1/2 sample rate up to 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 272 mW @ 170 MSPS 364 mW @ 250 MSPS Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code)

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane 2 W total power at 3 GSPS (default settings) Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 4 integrated digital downconverters 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither AEQ-Q100 qualified for automotive applications

12-Bit, 1200 MSPS DACs Features: Pin-compatible family Excellent dynamic performance LVDS data interface with on-chip 100 Ω terminations Built-in self test LVDS sampling integrity LVDS-to-DAC data transfer integrity Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz) 1.8/3.3 V dual-supply operation Adjustable analog output 8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω) On-chip 1.2 V reference 160-lead chip scale ball grid array (CSP_BGA) package