2, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier Features: Digital input stereo, high efficiency Class-D amplifier Operates from a single 4.5 V to 16.5 V supply State-of-the-art, proprietary, filterless - modulation 106.5 dB SNR at PO = 8.1 W, RL = 8 , AV = 19 dB, PVDD = 12 V, A weighted 0.004% THD + N at 5 W into 8 38.5 V rms output voltage noise, f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 Pop and clickless on and off sequence 2 14.67 W output at 12 V supply to 4 loads at <1% THD + N 2 14.4 W output at 16 V supply to 8 loads at <1% THD + N Mono mode for increased maximum output power 1 49.69 W output at 16 V supply to 2 loads at <1% THD + N Support for low impedance loads As low as 3 Ω/5 μH in stereo mode As low as 2 Ω/5 μH in mono mode High power efficiency 93.8% efficiency into an 8 Ω load 90.6% efficiency into a 4 Ω load 12.34 mA quiescent current with single 12 V PVDD supply Single-supply operation with internal LDOs or option to use an external 5 V and 1.8 V supply for lowest power consumption I2C control and hardware modes with up to 16 pin-selectable slots/addresses Supported sample rates from 8 kHz to 192 kHz with 24-bit resolution Multiple PCM audio serial data formats TDM slave with support for up to 16 devices on a single bus I2S or left justified slave Adjustable full-scale output tailored for many PVDD sources 2- and 3-cell Li-Ion batteries Digital volume control with selectable smooth ramp Automatic power-down function Supply monitoring automatic gain control (AGC) function reduces system brownout Standalone operational mode without I2C Temperature sensor with 1°C step readout via I2C Short-circuit, undervoltage, and thermal protection Thermal early warning Power-on reset PVDD sensing ADC 40-lead, 6 mm × 6 mm LFCSP with thermal pad

9 GHz to 12 GHz, GaAs, MMIC, I/Q Downconverter Features: Conversion gain: 11 dB (typical) at IFOUT = 100 MHz Image rejection: 25 dB (typical) at IFOUT = 100 MHz LO to RF isolation: 46 dB (typical) LO to IF isolation: 26 dB (typical) IF output frequency: dc to 3.5 GHz 32-lead, 4.9 mm × 4.9 mm ceramic leadless chip carrier

5.6 GHz to 8.6 GHz, GaAs, MMIC, I/Q Downconverter Features: Conversion gain: 13 dB typical Image rejection: 32 dBc typical Input P1dB compression: −6 dBm typical Input IP3: 3 dBm typical, 6.0 GHz to 8.6 GHz Noise figure: 2 dB typical LO to RF isolation: 48 dBm typical LO to IF isolation: 13 dBm typical RF to IF isolation: 10 dBm typical Amplitude balance: 0.2 dB typical Phase balance: −2° typical RF return loss: 10 dB typical LO return loss: 15 dB typical IF return loss: 15 dB typical Exposed paddle, 4 mm × 4 mm, 24-lead, LFCSP

5.6 GHz to 8.6 GHz, GaAs, MMIC, I/Q Downconverter Features: Conversion gain: 13 dB typical Image rejection: 32 dBc typical Input P1dB compression: −6 dBm typical Input IP3: 3 dBm typical, 6.0 GHz to 8.6 GHz Noise figure: 2 dB typical LO to RF isolation: 48 dBm typical LO to IF isolation: 13 dBm typical RF to IF isolation: 10 dBm typical Amplitude balance: 0.2 dB typical Phase balance: −2° typical RF return loss: 10 dB typical LO return loss: 15 dB typical IF return loss: 15 dB typical Exposed paddle, 4 mm × 4 mm, 24-lead, LFCSP

Quad-Channel Digital Isolator (3/1 Channel Directionality) Features: Qualified for automotive applications Low power operation Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics High common-mode transient immunity: >25 kV/μs See data sheet for additional features

5 KV rms Isolated Precision Half-Bridge Driver, 4 A Output Features: 4 A peak output current Working voltage High-side or low-side relative to input: 537 V peak High-side to low-side differential: 800 V peak High frequency operation: 1 MHz maximum  3.3 V to 5 V CMOS input logic 4.5 V to 18 V output drive  UVLO at 2.5 V VDD1 ADuM3223A/ADuM4223A UVLO at 4.1 V VDD2 ADuM3223B/ADuM4223B UVLO at 7.0 V VDD2 ADuM3223C/ADuM4223C UVLO at 11.0 V VDD2 Precise timing characteristics  54 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching CMOS input logic levels  High common-mode transient immunity:>25 kV/μs Enhanced system-level ESD performance per IEC 61000-4-x  High junction temperature operation: 125°C  Thermal shutdown protection  Default low output Safety and regulatory approvals ADuM4223 wide-body, 16-lead SOIC UL recognition per UL 1577  5000 V rms for 1 minute SOIC long package  CSA Component Acceptance Notice 5A  VDE certificate of conformity  DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak  Qualified for automotive applications

Clock-Tunable, Quad Second Order, Filter Building Blocks Features: Four Identical 2nd Order Filter Sections in an SSOP Package 2nd Order Section Center Frequency Error: ±0.3% Typical and ±0.8% Maximum Low Noise per 2nd Order Section, Q ≤ 5: LTC1068-200 50µVRMS, LTC1068 50µVRMS  LTC1068-50 70µVRMS, LTC1068-25 90µVRMS Low Power Supply Current: 4.5mA, Single 5V, LTC1068-50 Operation with ±5V Power Supply, Single 5V Supply or Single 3.3V Supply

Low Noise, 0.5% Tolerance, 5MHz to 28MHz, Pin Configurable Filter/ADC Driver Features: Pin Configurable Gain and Filter Response Up to 28MHz Few External Components Required Resistors Trimmed to 0.5% Typical Capacitors Trimmed to 0.5% Typical Very Low Noise: 80dB S/N in 100MHz Bandwidth Very Low Distortion (2VP-P): 1MHz: –100dBc 2nd, –123dBc 3rd 10MHz: –72dBc 2nd, –103dBc 3rd Adjustable Output Common Mode Voltage Rail-to-Rail Output Swing Power Configurability and Low Power Shutdown Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package

AD5231 - 10-Bit EEMEM Digital POT

IC IF DIGITIZING SUBSYSTEM 48LQFP; IC Function:IF Digitizing Subsystem; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; IC Package Type:LQFP; No. of Pins:48Pins; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Each; Product Range:-; Automotive Qualification Standard:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (20-Jun-2016)