General Purpose Digital Isolator 2500Vrms 4 Channel 10Mbps 25kV/µs CMTI 16-SOIC (0.295", 7.50mm Width)

Video Switch ICs 2:1 DVI/HDMI Switch

3GHz HDMI 2:2 cross point Transceiver with On-Screen Display Features: 2-input, 2-output cross-point HDMI® transceiver HDMI support 3 GHz video support (e.g. 4k × 2k) Audio return channel (ARC) 3D TV support Content type bits CEC 1.4-compatible Extended colorimetry High-Bandwidth Digital Content Protection (HDCP 1.4) Ultralow jitter digital PLL (100% deskew) Character- and icon-based on-screen display (OSD) 3D OSD overlay on all mandatory 3D formats Support for OSD overlay on 3 GHz video formats HDCP repeater support: up to 127 KSVs supported 300 MHz maximum TMDS clock frequency (up to 4k × 2k) 48-, 36-, 30-bit deep colour input modes supported See data sheet for additional features

Clock-Tunable, Quad Second Order, Filter Building Blocks Features: Four Identical 2nd Order Filter Sections in an SSOP Package 2nd Order Section Center Frequency Error: ±0.3% Typical and ±0.8% Maximum Low Noise per 2nd Order Section, Q ≤ 5: LTC1068-200 50µVRMS, LTC1068 50µVRMS  LTC1068-50 70µVRMS, LTC1068-25 90µVRMS Low Power Supply Current: 4.5mA, Single 5V, LTC1068-50 Operation with ±5V Power Supply, Single 5V Supply or Single 3.3V Supply

Ultracompact 1.5 A Thermoelectric Cooler (TEC) Controller Features: Patented high efficiency single inductor architecture Integrated low RDSON MOSFETs for the TEC controller TEC voltage and current operation monitoring No external sense resistor required Independent TEC heating and cooling current limits settings Programmable maximum TEC voltage 2.0 MHz PWM driver switching frequency External synchronization Two integrated zero drift, rail-to-rail chopper amplifiers Capable of NTC or RTD thermal sensors 2.50 V reference output with 1% accuracy Temperature lock indicator Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a 24-lead, 4 mm × 4 mm LFCSP AEC-Q100 qualified for automotive applications

5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter Features: Wideband RF output frequency range: 5.9 GHz to 23.6 GHz Two upconversion modes Direct conversion from baseband I/Q to RF Single sideband upconversion from real IF LO input frequency range: 5.4 GHz to 14 GHz LO doubler for up to 28 GHz Matched 100 Ω balanced RF output, LO input, and IF input High impedance baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator and power detector for Tx power control Programmable via 4-wire SPI interface 32-lead, 5 mm × 5 mm LFCSP microwave packaging

Four ADC, Two DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing 28-bit SigmaDSP audio processing core Visually programmable using SigmaStudio Up to 50 MIPS performance Low latency, 24-bit ADCs and DACs 96 dB SNR (signal through PGA and ADC with A-weighted filter) 105 dB combined SNR (signal through DAC and headphone with A-weighted filter) Serial port fSYNC frequency from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 4 single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs 2 analog differential audio outputs, configurable as either line output or headphone driver PLL supporting any input clock rate from 30 kHz to 27 MHz Full-duplex, 4-channel ASRCs 2, 16-channel serial audio ports supporting I2S, left justified, or up to TDM16 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.9 V typical Low power (11.079 mW for typical stereo ANC settings) I2C and SPI control interfaces, self boot from I2C EEPROM Flexible GPIO 42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP

A2B Main 4xPDM XCVR wI2S/TDM Features:A2B BUS FEATURES Line topology Single main node, multiple subordinate nodes Up to 15 m between nodes and up to 40 m overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency node to node communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power subordinate nodes Configurable with SigmaStudio/SigmaStudio+ graphical software tool AEC-Q100 qualified for automotive applicationsA2B TRANSCEIVER FEATURES Configurable A2B bus main node or subordinate node Programmable via I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

Single/Dual, +15 V/5 V, 256-Position, I2C-Compatible Digital Potentiometer Features: AD5280: 1 channel AD5282: 2 channels 256 positions +10 V to +15 V single supply; ±5.5 V dual-supply operation 20 kΩ, 50 kΩ, 200 kΩ fixed terminal resistance Low temperature coefficient: 30 ppm/°C Power-on midscale preset1  Programmable reset Operating temperature: −40°C to +85°C I2C-compatible interface

SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs Features: 28-/56-bit, 50 MIPS digital audio processor 2 ADCs: SNR of 100 dB, THD + N of −83 dB 4 DACs: SNR of 104 dB, THD + N of −90 dB Complete standalone operation Self-boot from serial EEPROM Auxiliary ADC with 4-input mux for analog control GPIOs for digital controls and outputs Fully programmable with SigmaStudio graphical tool 28-bit × 28-bit multiplier with 56-bit accumulator for full double-precision processing Clock oscillator for generating master clock from crystal See Data Sheet for Additional Information