Digital Signal Processors & Controllers - DSP, DSC 533MHz Convergent Multimedia Proc w/MDDR

7B34 - IC Controller 14V - 35V Module Tray

SmartMesh WirelessHART wireless sensor networks are self managing, low power networks built from wireless nodes called motes. The LTC5800-WHM is the WirelessHART Mote-on-Chip™ integrated circuit in the Eterna® family of IEEE 802.15.4 System-on-Chip (SoC) solutions, featuring a highly integrated, low power radio design by Analog Devices as well as an ARM Cortex-M3 32-bit microprocessor running our embedded SmartMesh WirelessHART networking software.With Analog Devices' time-synchronized WirelessHART networks all motes in the network may route, source or terminate data while providing many years of battery powered operation. The SmartMesh WirelessHART software provided with the LTC5800-WHM is fully tested and validated, and is readily configured via a software Application Programming Interface.SmartMesh WirelessHART motes deliver a highly flexible network with proven reliability and low power performance in an easy-to-integrate platform. Network Features Feature Benefit Time Synchronized, Channel Hopping Communications >99.999% network reliability in even the most challenging RF environments Sub 50 µA Routers Can build out a network without any line powered devices. Flexibility to be line powered or energy harvested if desired. Secure Mesh with 128-bit AES Encryption NIST Certified Security. Compromise of one node does not compromise network. Standards-based Compliant to international standard IEC 62591 (WirelessHART) Highly Accurate Time Stamping Time stamping on every node is available to applications with millisecond accuracy Device Features Feature Benefit Industry-Leading Low Power Radio Technology 4.5mA to Receive a Packet 5.4mA to Transmit at 0dBm 9.7mA to Transmit at 8dBm Pre-engineered RF RF elements include an on-chip power amplifier and are pre-tuned for optimized performance, including temperature compensation, saving development time. Energy Harvesting Support Very low power design enables motes to be powered by a wide variety of energy harvesters ApplicationsLearn more about SmartMesh applications.

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21478 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21478 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21478 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The BF592 is the low cost entry point into the Blackfin portfolio of processors. With core clock speeds of 200 and 400 MHz and a peripheral set including two SPORT’s, a PPI, two SPI’s, four general purpose counters and a factory-programmed Instruction ROM block containing the VDK RTOS and C-runtime libraries, the BF592 is feature and cost optimized for compute intensive industrial, automotive, and general purpose applications that do not require external memory or executable flash. The BF592 is offered in a low cost 9×9mm LFCSP package in commercial and industrial temperature grades as well as automotive qualified. 

The ADSP-BF547 processors were specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. For applications that require additional external memory, the ADSP-BF547 family provides product variants specifically designed to interface to either Standard DDR1 or 1.8V Low-Power DDR memory devices.IP protection has become a necessary part of today’s embedded applications. The ADSP-BF54x provides a security scheme that balances flexibility and upgradeability with performance through the inclusion of a firmware based solution including OTP memory to enable users to implement private keys for secure access to program code.The ADSP-BF547 provides peripheral flexibility to complement its high performance processing. These rich system level peripherals are well suited for Advanced Vehicle Infotainment and Industrial multimedia applications where multiple standards are prevalent and system performance is required.To enhance connectivity, a High Speed USB On-the-Go (HS USB OTG) module with Integrated PHY has been integrated along with an 8/16-bit Host DMA Interface. These system level peripherals, along with standard serial connections provided by multiple on-chip SPORT, SPI, UART, and TWI interfaces, provide glue-less interfaces to multiple off chip devices including consumer and communication products, Bluetooth, and other application specific interfaces. This level of integration is perfect for the emerging and constantly changing products and standards in the car infotainment and multimedia segments.For interfacing off chip to storage media including hard drives, CD/DVD-drives, and NAND Flash products, the ADSP-BF547 has implemented a SD/SDIO controller, ATAPI-6 controller, and an 8/16-bit NAND flash controller.Many multimedia enhancements have also been included on the ADSP-BF547 to offload processor MIPS through hardware integration, expand display capabilities, and shorten customer development time. The multiple Enhanced Parallel Peripheral Interfaces that support ITU-R BT.656 Video Formats now can also drive 18/24-bit LCD displays. A Hardware acceleration block, the Pixel Compositor, has been developed to execute overlay, color conversion and alpha blending. This block significantly reduces processor core overhead associated with software RGB-YUV color conversion and alpha blending.For human interface capability, the ADSP-BF547 provides a 32-bit up/down counter that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. An 8x8 Keypad interface is also included.

The Blackfin® Processor family has been expanded to address the ever-increasing need for pervasive embedded network connectivity. This connectivity is powerful when utilized in conjunction with the high performance 16-/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the Dynamic Power Management (DPM) functionality. System designers can take advantage of the combined control and signal processing capabilities of the processor core across a wide range of end applications through the scalability of the pin and code compatibility of these new family members. The ADSP-BF536 and ADSP-BF537 are a functional extension of the popular ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors, and they are ideally suited for a variety of networked applications. The ADSP-BF537 is the higher performance series member, with more embedded memory enabling higher throughput needs for embedded applications suchas video security/surveillance and industrial-environment-based distributed control/factory automation applications. The ADSP-BF536 offers exceptional performance and is designed for low cost connected devices such as remote monitoring devices, VoIP, point-of-sale terminals, and biometrics/security applications. Both devices are ideally suited for a broadrange of industrial, instrumentation, medical, and consumer appliance applications— allowing for scalability based upon the required network bandwidth and mix of control, plus signal processing needed in the end product.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the arm® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.By integrating a set of industry leading system peripherals and memory, the arm® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADV3002 is a complete HDMI™/DVI link switch featuring equalized transition minimized differential signaling (TMDS) inputs, ideal for systems with long cable runs. The ADV3002 includes bidirectional buffering for the DDC bus and CEC line, with integrated pull-up resistors for the CEC line. Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports.The ADV3002 is provided in a space-saving, 80-lead LQFP surface-mount Pb-free plastic package and is specified to operate over the 0°C to 85°C temperature range.PRODUCT HIGHLIGHTS Input cable equalizer enables use of long cables at the input. For a 24 AWG cable, the ADV3002 compensates for more than 20m at data rates up to 3 Gbps. Auxiliary multiplexer isolates and buffers the DDC bus and the CEC line, increasing total system capacitance limit. EDID replication eliminates the need for multiple EDID EEPROMs. EDID can be loaded from a single external EEPROM or from a system microcontroller. 5 V power combiner powers the EDID replicator and CEC buffer when local system power is off. Integrated hot plug detect pulse low on channel switch with programmable pulse width or direct manual control.APPLICATIONS Advanced television (HDTV) sets Projectors A/V receivers Set-top boxes

The Blackfin processor family is extended further into the industrial and instrumentation market with the availability of an on chip eMAC, a 3-phase PWM generation unit and a quadrature encoder. The high performance 16/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of connected applications, including motor control, power line monitoring, biometrics, pro-audio and femto cells. The embedded eMAC of the BF516 coupled with a 400MHz CPU and a plethora of other peripherals make the BF516 the most attractive choice for demanding network connected systems.The VoIP challenge to the embedded-system designer is to choose a processing solution that is cost-effective, easy to deploy and scaleable in performance across market spaces. A “sweet spot” embedded-solution approach is to design with a platform that can implement a low channel count basic VoIP solution, yet retain sufficient capacity for value added capabilities and services – such as video, music, imaging and system control. Unlike traditional VoIP embedded solutions that utilize two processor cores to provide VoIP functionality, the ADSP-BF516 provides a convergent solution in a unified core architecture that allows voice and video signal processing concurrent with RISC MCU processing to handle network and user-interface demands. This unique ability to offer full VoIP functionality on a single convergent processor provides for a unified software development environment, faster system debugging and deployment, and lower overall system cost.The BF516 also brings ultra low power and a removable storage interface covering SDIO, CE-ATA and eMMC for portable devices.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF516 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.