The ADSP-CM408F Mixed-Signal Control Processor integrates dual high precision 16 bit ADCs and an ARM® Cortex-M4TM processor core with floating-point unit operating at 240 MHz core clock frequency and integrating 384KB of SRAM memory, 2M byte of flash memory, and accelerators and peripherals optimized for motor control, photo-voltaic (PV) inverter control and other embedded control applications.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the arm® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.By integrating a set of industry leading system peripherals and memory, the arm® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The AD8197 is an HDMI™/DVI switch featuring equalized TMDS® inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. Flexible channel bundling modes (for both the TMDS channels and the auxiliary signals) allow the AD8197 to be configured as a 4:1 single HDMI/DVI link switch, a dual 8:1 switch, or a single 16:1 switch.The AD8197 is provided in a 100-lead LQFP, Pb-free, surface-mount package, specified to operate over the −40°C to +85°C temperature range. ul { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:15px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;} ol { margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:25px; padding-top:0px; padding-right:0px; padding-bottom:10px; padding-left:0px;} li { padding-top:0px; padding-right:0px; padding-bottom:5px; padding-left:0px; margin-top:0px; margin-right:0px; margin-bottom:0px; margin-left:0px;}Product Highlights Supports data rates up to 2.25 Gbps, enabling 1080p deep color (12-bit color) HDMI formats, and greater than UXGA (1600 × 1200) DVI resolutions. Input cable equalizer enables use of long cables at the input (more than 20 meters of 24 AWG cable at 2.25 Gbps). Auxiliary switch routes a DDC bus and two additional signals for a single-chip, HDMI 1.3 receive-compliant solution.Applications Multiple input displays Projectors A/V receivers Set-top boxes Advanced television (HDTV) sets Data Sheet, Rev. 0, 1/07

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21478 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21478 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21478 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21479 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21479 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21479 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs. Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The BF504 is a low cost member of the Blackfin portfolio of processors. With a 400 MHz core clock speed and a unique peripheral set including two three-phase PWM units, an ADC Control Module, two SPI’s, two SPORT’s, a CAN controller, a PPI, eight general purpose counters and a Removable Storage Interface, the BF504 is feature and cost optimized for compute intensive industrial and general purpose applications that do not require external memory or executable flash. The BF504 is offered in a low cost 12 × 12mm LFCSP package in commercial and industrial temperature grades.

The ADSP-BF525 offers up to 600 MHz performance and up to 1200 MMACs. This processor core is supported by an advanced DMA controller supporting one-and two-dimensional DMA transfers between on-chip memory, off-chip memory, and system peripherals. The combination of the processor core speed and the DMA controller allows for efficient processing of audio, voice, video, and image data.The ADSP-BF525 provides peripheral flexibility to complement its high performance processing. The HS USB OTG host direct memory access (HDMA) and NAND flash controller are just a few of the peripheral options on the ADSP-BF525 family—not to mention the availability of up to 48 GPIO ports.For applications where product differentiation represents a challenge for securing market leadership, the ADSP-BF525 enables developers to provide features and benefits to augment their product offerings without compromising cost or power. The scalability of the ADSP-BF525 makes it an ideal candidate for Premium Audio Players where differentiation of features can be realized without sacrificing system cost. Where the diversity of Multimedia applications and content security are key attributes the ADSP-BF525 provides processing flexibility and Lockbox™ Secure Technology to enable users to develop freely and without bounds.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF525 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

The high performance 16/32-bit Blackfin embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of portable applications, including consumer, communications and industrial/instrumentation.With the combination of peripherals which enable glue-less connectivity to networked devices such as Ethernet or WiFi 802.11 a/b/g modules and power efficient signal processing, the ADSP-BF527 is well suited to IP connected applications such as VoIP Phone or IP Camera.The VoIP challenge to the embedded-system designer is to choose a processing solution that is cost-effective, easy to deploy and scaleable in performance across market spaces. A “sweet spot” embedded-solution approach is to design with a platform that can implement a low channel count basic VoIP solution, yet retain sufficient capacity for value added capabilities and services – such as video, music, imaging and system control. Unlike traditional VoIP embedded solutions that utilize two processor cores to provide VoIP functionality, the ADSP-BF527 provides a convergent solution in a unified core architecture that allows voice and video signal processing concurrent with RISC MCU processing to handle network and user-interface demands. This unique ability to offer full VoIP functionality on a single convergent processor provides for a unified software development environment, faster system debugging and deployment, and lower overall system cost.IP protection has become a necessary part of today’s embedded computing applications. The ADSP-BF527 provides a security scheme which balances flexibility and upgradeability with performance through the inclusion of a firmware-based solution including OTP (One Time Programmable) memory to enable users to implement private keys for secure access to program code.

The ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF531 / ADSP-BF532 / ADSP-BF533 processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.PERIPHERALS Parallel peripheral interface PPI, supporting ITU-R 656 video data formats 2 dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels 2 memory-to-memory DMAs 8 peripheral DMAs SPI-compatible port Three 32-bit timer/counters with PWM support Real-time clock and watchdog timer 32-bit core timer Up to 16 general-purpose I/O pins (GPIO) UART with support for IrDA Event handler Debug/JTAG interface On-chip PLL capable of frequency multiplication