Laser Drivers 3.3V 622Mbps SDH/SONET

3.3 V Dual-Loop 50 Mbps to 3.3 Gbps Laser Diode Driver

4-Channel, LVDS, Dual-Output, Laser Diode Driver with Oscillator Features: Dual, current-controlled output current sources with 4 input channels TTL-selectable output Stable on-chip oscillators with independent frequency and amplitude control TTL- or LVDS-selectable write channel enables negative logic Independent TTL oscillator enables positive logic 170 mA minimum output current for the read channel 510 mA minimum output current for Write Channel 1 330 mA minimum output current for Write Channel 2 165 mA minimum output current for Write Channel 3 950 mA typical total output current Typical rise time/fall time of  0.8 ns Low power consumption Single 5 V power supply (±10%)

600mA Universal Multi-Output LED/CAM Driver Features: Low Noise, Multi-Mode Charge Pump (1x, 1.5x, 2x) Provides Up to 91% Efficiency Slew Limited Switching Reduces Conducted and Radiated Noise (EMI) Up to 600mA Total Output Current Twelve 28mA Universal Current Sources with 64-Step Linear Brightness Control 425mA CAM LED Current Source with 16-Step Linear Brightness Control and 2-Second High Current Safety Timer Independent On/Off, Brightness Level, Blinking and Gradation Control for Each Current Source Using 2-Wire I2C Interface Internal Current Reference Two I2C Addresses are Available (LTC3207 00110110, LTC3207-1 00110100) Configurable ENU Pin for Asynchronous LED On/Off Control Automatic or Forced Mode Switching Internal Soft-Start Limits Inrush Current Short-Circuit/Thermal Protection 4mm × 4mm 24-Pin QFN Plastic Package

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

The AD9984A is a complete 10-bit, 170 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 170 MSPS encode rate capability and full power analog bandwidth of 300 MHz support all HDTV video modes up to 1080p, as well as graphics resolutions up to UXGA (1600 × 1200 at 60 Hz). The AD9984A includes a 170 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 1.8 V power supply and an analog input. Three-state CMOS outputs can be powered from 1.8 V to 3.3 V. The AD9984A on-chip PLL generates a sample clock from the tri-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 170 MHz. With internal coast generation, the PLL maintains its output frequency in the absence of a sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained. The auto-offset feature can be enabled to automatically restore the signal reference levels and calibrate out any offset differences between the three channels. The auto channel-to-channel gain-matching feature can be enabled to minimize any gain mismatches between the three channels. The AD9984A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or can be provided by the user through the CLAMP input pin. Fabricated in an advanced CMOS process, the AD9984A is provided in a space-saving, Pb-free, 80-lead low profile quad flat package (LQFP) or 64-lead lead frame chip scale package (LFCSP) and is specified over the 0°C to 70°C temperature range.APPLICATIONSAdvanced TVs Plasma display panels LCDTV HDTV RGB graphics processing LCD monitors and projectors Scan converters

LED Lighting Drivers 4 Channel High Current LED Driver with Adaptable Power Control

SPECIALTY / SPECIALIZED INTERFACES;

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